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| user?s manual v850e1 32-bit microprocessor core architecture document no. u14559ej2v0um00 (2nd edition) date published march 2001 j cp(k) printed in japan 1999 ?
user?s manual u14559ej2v0um 2 [memo] user?s manual u14559ej2v0um 3 summary of contents chapter 1 general ........................................................................................................... ................ 19 chapter 2 register set ..................................................................................................... ............ 22 chapter 3 data type ........................................................................................................ ............... 36 chapter 4 address space.................................................................................................... ......... 40 chapter 5 instruction ....................................................................................................... ............. 46 chapter 6 interrupt and exception ..................................................................................... 166 chapter 7 reset............................................................................................................. .................. 175 chapter 8 pipeline .......................................................................................................... ................ 177 appendix a instruction list................................................................................................ ....... 200 appendix b instruction opcode map..................................................................................... 214 appendix c differences with architecture of v850 cpu ........................................... 213 appendix d instructions added for v850e1 cpu compared with v850 cpu ....... 221 appendix e index ............................................................................................................ .................. 223 user?s manual u14559ej2v0um 4 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. v850 family, v850e/ma1, v850e/ma2, v850e/ia1, and v850e/ia2 are trademarks of nec corporation. windows is either a registered trademark or a trademark of microsoft corporation in the united states and/or other countries. user ? s manual u14559ej2v0um 5 the export of these products from japan is regulated by the japanese government. the export of some or all of these products may be prohibited without governmental license. to export or re-export some or all of these products from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. m8e 00. 4 the information in this document is current as of january, 2001. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec's data sheets or data books, etc., for the most up-to-date specifications of nec semiconductor products. not all products and/or types are available in every country. please check with an nec sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec. nec assumes no responsibility for any errors that may appear in this document. nec does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. nec assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec endeavours to enhance the quality, reliability and safety of nec semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. nec semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec semiconductor products is "standard" unless otherwise expressly specified in nec's data sheets or data books, etc. if customers wish to use nec semiconductor products in applications not intended by nec, they must contact an nec sales representative in advance to determine nec's willingness to support a given application. (note) (1) "nec" as used in this statement means nec corporation and also includes its majority-owned subsidiaries. (2) "nec semiconductor products" means any semiconductor product developed or manufactured by or for nec (as defined above). ? ? ? ? ? ? user?s manual u14559ej2v0um 6 regional information some information contained in this document may vary from country to country. before using any nec product in your application, piease contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.l. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-3067-5800 fax: 01-3067-5899 nec electronics (france) s.a. madrid office madrid, spain tel: 091-504-2787 fax: 091-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. novena square, singapore tel: 253-8311 fax: 250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec do brasil s.a. electron devices division guarulhos-sp, brasil tel: 11-6462-6810 fax: 11-6462-6829 j01.2 user?s manual u14559ej2v0um 7 major revision in this edition (1/2) page description throughout ? addition of following products (under development) to target products nb85et, NU85E, NU85Et, pd703108, 703114, 70f3114, 703116 ? deletion of following product from target products pd703117 ? change of following products from ?under development? to ?developed? pd703106, 703107, 70f3107 p.22 change of note in figure 2-1 registers p.24 change of table 2-2 system register numbers p.27 addition of note to figure 2-6 program status word (psw) p.29 addition of note to section 2.2.6 exception/debug trap status saving registers (dbpc, dbpsw) p.30 change of caution in section 2.2.8 debug interface register (dir) p.32 change of caution in section 2.2.9 breakpoint control registers 0 and 1 (bpc0, bpc1) p.32 change of figure 2-11 breakpoint control registers 0 and 1 (bpc0, bpc1) p.33 change of caution in section 2.2.10 program id register (asid) p.34 change of caution in section 2.2.11 breakpoint address setting registers 0 and 1 (bpav0, bpav1) p.34 change of caution in section 2.2.12 breakpoint address mask registers 0 and 1 (bpam0, bpam1) p.35 change of caution in section 2.2.13 breakpoint data setting registers 0 and 1 (bpdv0, bpdv1) p.35 change of caution in section 2.2.14 breakpoint data mask registers 0 and 1 (bpdm0, bpdm1) p.53 addition of caution to section 5.2 (10) debug function instructions p.69 addition of caution to dbret in section 5.3 instruction set p.70 addition of caution to dbtrap in section 5.3 instruction set p.161 change of and adding note to table 5-6 list of number of instruction execution clock cycles (nb85e, nb85et, NU85E, and NU85Et) p.164 change of note to table 5-7 list of number of instruction execution clock cycles (v850e/ma1, v850e/ma2, v850e/ia1, and v850e/ia2) p.166 addition of note to table 6-1 interrupt/exception codes p.172 addition of caution to section 6.2.3 debug trap p.180 addition of remark and example to section 8.1.2 2-clock branch p.181 addition of caution to section 8.1.3 efficient pipeline processing p.182 correction of description in section 8.2 (2) v850e/ma1, v850e/ma2, v850e/ia1, v850e/ia2 p.182 correction of description in section 8.2.1 (2) sld instructions p.183 correction of description in section 8.2.3 multiply instructions p.184 addition of remark to section 8.2.4 (3) divide instructions p.187 correction of description in section 8.2.8 (2) tst1 instruction p.188 addition of remark to section 8.2.9 (3) di, ei instructions p.190 addition of caution to section 8.2.9 (7) nop instruction p.193 addition of section 8.3 pipeline disorder p.197 addition of section 8.4 additional items related to pipeline p.201 addition of note to table a-1 instruction function list (in alphabetical order) pp.211, 213 addition of note to table a-2 instruction list (in format order) user?s manual u14559ej2v0um 8 major revision in this edition (2/2) page description p.214 correction of figure in appendix b (2) 32-bit format instruction p.215 addition of remark to appendix b [a] opcode p.217 addition of remark to appendix b [e] expansion 1 (sub-opcode) pp.219, 220 addition of note to appendix c differences with architecture of v850 cpu p.222 addition of note to table d-1 instructions added to v850e1 cpu and v850 cpu instructions with same instruction code the mark shows major revised points. 9 user?s manual u14559ej2v0um preface target readers this manual is intended for users who wish to understand the functions of the v850e1 cpu core for designing application systems using the v850e1 cpu core. products incorporating v850e1 cpu core nb85e note , nb85et note , NU85E note , NU85Et note v850e/ma1? : pd703103 note , 703105 note , 703106, 703107, 70f3107 v850e/ma2? : pd703108 note v850e/ia1? : pd703116 note , 70f3116 note v850e/ia2? : pd703114 note , 70f3114 note note under development purpose this manual is intended for users to understand the architecture of the v850e1 cpu core described in the organization below. organization this manual contains the following information: ? register set data type instruction format and instruction set interrupt and exception pipeline how to use this manual it is assumed that the reader of this manual has general knowledge in the fields of electrical engineering, logic circuits, and microcontrollers. to learn about the hardware functions, read user?s manual hardware of each product. to learn about the functions of a specific instruction in detail, read chapter 5 instruction . conventions data significance: higher digits on the left and lower digits on the right active low representation: b (b is appended to pin or signal name) note : footnote for item marked with note in the text caution : information requiring particular attention remark : supplementary information numerical representation: binary ... or b decimal ... hexadecimal ... h prefix indicating the power of 2 (address space, memory capacity): k (kilo): 2 10 = 1,024 m (mega): 2 20 = 1,024 2 g (giga): 2 30 = 1,024 3 10 user?s manual u14559ej2v0um related documents the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. ? ? ? ? device related documents document name document no. nb85e user?s manual hardware a13971e nb85et user?s manual hardware a14342e NU85E user?s manual hardware a14874e NU85Et user?s manual hardware a15015e v850e/ma1 user?s manual hardware u14359e v850e/ma2 user?s manual hardware u14980e v850e/ia1 user?s manual hardware u14492e v850e/ia2 user?s manual hardware u15195e ? ? ? ? development tool related documents document name document no. ie-v850e-mc, ie-v850e-mc-a (in-circuit emulator) u14487e ie-v850e-mc-em1-a (peripheral i/o board for v850e1) to be prepared ie-v850e-mc-em1-b, ie-v850e-mc-mm2 (peripheral i/o board for v850e1) u14482e ie-703107-mc-em1 (peripheral i/o board for v850e/ma1, v850e/ma2) u14481e ie-703116-mc-em1(peripheral i/o board for v850e/ia1) to be prepared ie-703114-mc-em1(peripheral i/o board for v850e/ia2) to be prepared operation u14568e c language u14566e project manager u14569e ca850 (ver. 2.30 or later) (c compiler package) assembly language u14567e id850 (ver. 2.20 or later) (integrated debugger) operation windows tm based u14580e sm850 (ver. 2.20 or later) (system simulator) operation windows based u14782e sm850 (ver. 2.00 or later) (system simulator) external part user open interface specifications u14873e fundamental u13430e installation u13410e rx850 (ver. 3.13 or later) (real-time os) technical u13431e fundamental u13773e installation u13774e rx850 pro (ver. 3.13) (real-time os) technical u13772e rd850 (ver. 3.01) (task debugger) u13737e rd850 pro (ver. 3.01) (task debugger) u13916e az850 (ver. 3.0) (system performance analyzer) u14410e pg-fp3 (flash memory programmer) u13502e 11 user?s manual u14559ej2v0um contents chapter 1 general ........................................................................................................... ................ 19 1.1 features .................................................................................................................... ..................... 20 1.2 internal configuration...................................................................................................... ............. 21 chapter 2 register set ..................................................................................................... ............ 22 2.1 program registers ........................................................................................................... ............. 23 2.2 system registers ............................................................................................................ .............. 24 2.2.1 interrupt status saving registers (eipc, eipsw) ........................................................................... ...25 2.2.2 nmi status saving registers (fepc, fepsw)................................................................................. ..26 2.2.3 exception cause register (ecr) ............................................................................................ ...........26 2.2.4 program status word (psw) ................................................................................................. ............27 2.2.5 callt caller status saving registers (ctpc, ctpsw) ....................................................................28 2.2.6 exception/debug trap status saving registers (dbpc, dbpsw) ......................................................29 2.2.7 callt base pointer (ctbp)................................................................................................. ............30 2.2.8 debug interface register (dir)............................................................................................ ..............30 2.2.9 breakpoint control registers 0 and 1 (bpc0, bpc1)......................................................................... 32 2.2.10 program id register (asid)............................................................................................... ................33 2.2.11 breakpoint address setting registers 0 and 1 (bpav0, bpav1).......................................................34 2.2.12 breakpoint address mask registers 0 and 1 (bpam0, bpam1)........................................................34 2.2.13 breakpoint data setting registers 0 and 1 (bpdv0, bpdv1) ............................................................35 2.2.14 breakpoint data mask registers 0 and 1 (bpdm0, bpdm1) .............................................................35 chapter 3 data type ........................................................................................................ ............... 36 3.1 data format ................................................................................................................. .................. 36 3.2 data representation ......................................................................................................... ............ 38 3.2.1 integer ................................................................................................................... ...........................38 3.2.2 unsigned integer .......................................................................................................... ....................38 3.2.3 bit ....................................................................................................................... ..............................38 3.3 data alignment.............................................................................................................. ................ 39 chapter 4 address space.................................................................................................... ......... 40 4.1 memory map .................................................................................................................. ................ 41 4.2 addressing mode ............................................................................................................. ............. 42 4.2.1 instruction address ....................................................................................................... ....................42 4.2.2 operand address........................................................................................................... ...................44 chapter 5 instruction ....................................................................................................... ............. 46 5.1 instruction format .......................................................................................................... .............. 46 12 user?s manual u14559ej2v0um 5.2 outline of instructions ..................................................................................................... .............50 5.3 instruction set ............................................................................................................. ..................54 add ............................................................................................................................ ....................................56 addi ........................................................................................................................... ....................................57 and ............................................................................................................................ ....................................58 andi ........................................................................................................................... ....................................59 bcond .......................................................................................................................... ...................................60 bsh ............................................................................................................................ ....................................62 bsw............................................................................................................................ ....................................63 callt.......................................................................................................................... ...................................64 clr1........................................................................................................................... ....................................65 cmov ........................................................................................................................... ..................................66 cmp............................................................................................................................ ....................................67 ctret.......................................................................................................................... ..................................68 dbret.......................................................................................................................... ..................................69 dbtrap ......................................................................................................................... ................................70 di ............................................................................................................................. .......................................71 dispose........................................................................................................................ ................................72 div............................................................................................................................ ......................................74 divh ........................................................................................................................... ....................................75 divhu.......................................................................................................................... ...................................77 divu ........................................................................................................................... ....................................78 ei ............................................................................................................................. .......................................79 halt........................................................................................................................... ....................................80 hsw ............................................................................................................................ ...................................81 jarl ........................................................................................................................... ....................................82 jmp............................................................................................................................ .....................................83 jr ............................................................................................................................. ......................................84 ld.b........................................................................................................................... .....................................85 ld.bu .......................................................................................................................... ...................................87 ld.h........................................................................................................................... .....................................89 ld.hu .......................................................................................................................... ...................................91 ld.w........................................................................................................................... ....................................93 ldsr ........................................................................................................................... ...................................95 mov............................................................................................................................ ....................................96 movea.......................................................................................................................... .................................97 movhi .......................................................................................................................... ..................................98 mul ............................................................................................................................ ....................................99 mulh........................................................................................................................... .................................100 mulhi.......................................................................................................................... .................................101 mulu........................................................................................................................... .................................102 nop ............................................................................................................................ ..................................103 not ............................................................................................................................ ..................................104 not1 ........................................................................................................................... .................................105 or ............................................................................................................................. ...................................106 13 user?s manual u14559ej2v0um ori ............................................................................................................................ ...................................107 prepare ........................................................................................................................ ............................108 reti ........................................................................................................................... ..................................110 sar ............................................................................................................................ ..................................112 sasf ........................................................................................................................... .................................113 satadd ......................................................................................................................... ..............................114 satsub ......................................................................................................................... ..............................115 satsubi ........................................................................................................................ ..............................116 satsubr........................................................................................................................ .............................117 set1 ........................................................................................................................... .................................118 setf ........................................................................................................................... .................................119 shl ............................................................................................................................ ..................................121 shr ............................................................................................................................ ..................................122 sld.b .......................................................................................................................... .................................123 sld.bu......................................................................................................................... ................................125 sld.h .......................................................................................................................... .................................127 sld.hu ......................................................................................................................... ...............................129 sld.w .......................................................................................................................... ................................131 sst.b .......................................................................................................................... .................................133 sst.h .......................................................................................................................... .................................135 sst.w .......................................................................................................................... ................................137 st.b ........................................................................................................................... ..................................139 st.h ........................................................................................................................... ..................................141 st.w ........................................................................................................................... .................................143 stsr ........................................................................................................................... .................................145 sub ............................................................................................................................ ..................................146 subr........................................................................................................................... .................................147 switch ......................................................................................................................... ..............................148 sxb ............................................................................................................................ ..................................149 sxh ............................................................................................................................ ..................................150 trap ........................................................................................................................... .................................151 tst............................................................................................................................ ...................................152 tst1........................................................................................................................... ..................................153 xor............................................................................................................................ ..................................154 xori........................................................................................................................... ..................................155 zxb ............................................................................................................................ ..................................156 zxh ............................................................................................................................ ..................................157 5.4 number of instruction execution clock cycles....................................................................... 158 chapter 6 interrupt and exception ..................................................................................... 166 6.1 interrupt servicing ......................................................................................................... ............. 167 6.1.1 maskable interrupt ........................................................................................................ ..................167 6.1.2 non-maskable interrupt .................................................................................................... ..............169 6.2 exception processing........................................................................................................ ......... 170 14 user?s manual u14559ej2v0um 6.2.1 software exception ........................................................................................................ .................170 6.2.2 exception trap............................................................................................................ .....................171 6.2.3 debug trap ................................................................................................................ ......................172 6.3 restoring from interrupt/exception processing ......................................................................173 6.3.1 restoring from interrupt and software exception ........................................................................... .173 6.3.2 restoring from exception trap and debug trap .............................................................................. .174 chapter 7 reset ............................................................................................................. ..................175 7.1 register status after reset ................................................................................................. .......175 7.2 starting up ................................................................................................................. ..................176 chapter 8 pipeline.......................................................................................................... .................177 8.1 features.................................................................................................................... ....................178 8.1.1 non-blocking load/store ................................................................................................... ...............179 8.1.2 2-clock branch ............................................................................................................ ....................180 8.1.3 efficient pipeline processing ............................................................................................. ..............181 8.2 pipeline flow during execution of instructions ......................................................................182 8.2.1 load instructions......................................................................................................... ....................182 8.2.2 store instructions ........................................................................................................ ....................183 8.2.3 multiply instructions ..................................................................................................... ...................183 8.2.4 arithmetic operation instructions......................................................................................... ............184 8.2.5 saturated operation instructions .......................................................................................... ...........185 8.2.6 logical operation instructions ............................................................................................ .............185 8.2.7 branch instructions ....................................................................................................... ..................185 8.2.8 bit manipulation instructions ............................................................................................. ..............187 8.2.9 special instructions...................................................................................................... ...................187 8.2.10 debug function instructions .............................................................................................. ..............192 8.3 pipeline disorder ........................................................................................................... ..............193 8.3.1 alignment hazard.......................................................................................................... ..................193 8.3.2 referencing execution result of load instruction .......................................................................... ...194 8.3.3 referencing execution result of multiply instruction...................................................................... ..195 8.3.4 referencing execution result of ldsr instruction for eipc and fepc ..........................................196 8.3.5 cautions when creating programs ........................................................................................... .......196 8.4 additional items related to pipeline ........................................................................................ .197 8.4.1 harvard architecture ...................................................................................................... .................197 8.4.2 short path ................................................................................................................ .......................198 appendix a instruction list ................................................................................................ .......200 appendix b instruction opcode map .....................................................................................214 15 user?s manual u14559ej2v0um appendix c differences with architecture of v850 cpu ........................................... 219 appendix d instructions added for v850e1 cpu compared with v850 cpu ....... 221 appendix e index ............................................................................................................ .................. 223 16 user?s manual u14559ej2v0um list of figures (1/2) figure no. title page 1-1 internal block diagram of v850e1 cpu ........................................................................................ ...................21 2-1 registers................................................................................................................... ........................................22 2-2 program counter (pc) ........................................................................................................ ..............................23 2-3 interrupt status saving registers (eipc, eipsw)............................................................................. ...............25 2-4 nmi status saving registers (fepc, fepsw) ................................................................................... .............26 2-5 exception cause register (ecr) .............................................................................................. .......................26 2-6 program status word (psw)................................................................................................... .........................27 2-7 callt caller status saving registers (ctpc, ctpsw).......................................................................... .......29 2-8 exception/debug trap status saving registers (dbpc, dbpsw) .................................................................. 29 2-9 callt base pointer (ctbp) ................................................................................................... .........................30 2-10 debug interface register (dir) ............................................................................................. ...........................30 2-11 breakpoint control registers 0 and 1 (bpc0, bpc1).......................................................................... .............32 2-12 program id register (asid) ................................................................................................. ............................33 2-13 breakpoint address setting registers 0 and 1 (bpav0, bpav1)................................................................ .....34 2-14 breakpoint address mask registers 0 and 1 (bpam0, bpam1) ................................................................... ...34 2-15 breakpoint data setting registers 0 and 1 (bpdv0, bpdv1)................................................................... .......35 2-16 breakpoint data mask registers 0 and 1 (bpdm0, bpdm1) ...................................................................... .....35 4-1 memory map.................................................................................................................. ...................................41 4-2 relative addressing......................................................................................................... .................................42 4-3 register addressing (jmp [reg1] instruction) ................................................................................ ...................43 4-4 based addressing (type 1) ................................................................................................... ...........................44 4-5 based addressing (type 2) ................................................................................................... ...........................45 4-6 bit addressing.............................................................................................................. .....................................45 6-1 maskable interrupt servicing format......................................................................................... .....................168 6-2 non-maskable interrupt servicing format ..................................................................................... .................169 6-3 software exception processing format........................................................................................ ..................170 6-4 illegal instruction code .................................................................................................... ...............................171 6-5 exception trap processing format ............................................................................................ ....................171 6-6 debug trap processing format................................................................................................ ......................172 6-7 restoration from interrupt/software exception processing format............................................................. ...173 6-8 restoration from exception trap/debug trap processing format ................................................................ .174 8-1 example of executing nine standard instructions............................................................................. .............177 8-2 pipeline configuration...................................................................................................... ...............................178 8-3 non-blocking load/store..................................................................................................... ...........................179 8-4 pipeline operations with branch instructions ................................................................................ .................180 8-5 parallel execution of branch instructions ................................................................................... ....................181 8-6 align hazard example ........................................................................................................ ............................193 8-7 example of execution result of load instruction ............................................................................. ..............194 17 user?s manual u14559ej2v0um list of figures (2/2) figure no. title page 8-8 example of execution result of multiply instruction......................................................................... .............. 195 8-9 example of referencing execution result of ldsr instruction for eipc and fepc ..................................... 196 18 user?s manual u14559ej2v0um list of tables table no. title page 2-1 program registers........................................................................................................... .................................23 2-2 system register numbers..................................................................................................... ...........................24 5-1 conventions of instruction format........................................................................................... .........................54 5-2 conventions of operation .................................................................................................... .............................54 5-3 conventions of opcode ....................................................................................................... .............................55 5-4 bcond instructions .......................................................................................................... ..................................61 5-5 condition codes ............................................................................................................. ................................120 5-6 list of number of instruction execution clock cycles (nb85e, nb85et, NU85E, and NU85Et)..................158 5-7 list of number of instruction execution clock cycles (v850e/ma1, v850e/ma2, v850e/ia1, and v850e/ia2) .............................................................................. .162 6-1 interrupt/exception codes ................................................................................................... ...........................166 7-1 register status after reset................................................................................................. ............................175 a-1 instruction function list (in alphabetical order)........................................................................... ..................200 a-2 instruction list (in format order) ......................................................................................... ..........................211 d-1 instructions added to v850e1 cpu and v850 cpu instructions with same instruction code ......................221 19 user?s manual u14559ej2v0um chapter 1 general real-time control systems are used in a wide range of applications, including: office equipment such as hdds (hard disk drives), ppcs (plain paper copiers), printers, and facsimiles, automobile electronics such as engine control systems and abss (antilock braking systems), and factory automation equipment such as nc (numerical control) machine tools and various controllers. the great majority of these systems conventionally employ 8-bit or 16-bit microcontrollers. however, the performance level of these microcontrollers has become inadequate in recent years as control operations have risen in complexity, leading to the development of increasingly complicated instruction sets and hardware design. as a result, the need has arisen for a new generation of microcontrollers operable at much higher frequencies to achieve an acceptable level of performance under today?s more demanding requirements. the v850 family? of microcontrollers was developed to satisfy this need. this family uses risc architecture that can provide maximum performance with simpler hardware, allowing users to obtain a performance approximately 15 times higher than that of the existing 78k/iii series and 78k/iv series of cisc single-chip microcontrollers at a lower total cost. in addition to the basic instructions of conventional risc cpus, the v850 family is provided with special instructions such as saturate, bit manipulate, and multiply/divide (executed by a hardware multiplier) instructions, which are especially suited for digital servo control systems. moreover, instruction formats are designed for maximum compiler coding efficiency, allowing the reduction of object code sizes. the v850e1 cpu is a 32-bit risc cpu core for asic, newly developed as the cpu core central to system lsi in the current age of system-on-a-chip. this core includes not only the control functions of the v850 cpu, the cpu core incorporated in the v850 family, but also supports data processing through its enhanced external bus interface performance, and the addition of features such as c language switch statement processing, table lookup branching, stack frame creation/deletion, data conversion, and other high-level language supporting instructions. in addition, because the instruction codes are upwardly compatible with the v850 cpu at the object code level, the software resources of systems that incorporate the v850 cpu can be used unchanged. chapter 1 general 20 user?s manual u14559ej2v0um 1.1 features (1) high-performance 32-bit architecture for embedded control number of instructions: 83 32-bit general registers: 32 load/store instructions in long/short format 3-operand instruction 5-stage pipeline of 1 clock cycle per stage hardware interlock on register/flag hazards memory space program space: 64 mb linear data space: 4 gb linear (2) special instructions saturation operation instructions bit manipulation instructions multiply instructions (on-chip hardware multiplier executing multiplication in 1, 2, or 4 clocks) 16 bits 16 bits 32 bits 32 bits 32 bits 32 bits or 64 bits chapter 1 general 21 user?s manual u14559ej2v0um 1.2 internal configuration the v850e1 cpu executes almost all instructions such as address calculation, arithmetic and logical operation, and data transfer in one clock by using a 5-stage pipeline. it contains dedicated hardware such as a multiplier (32 32 bits) and a barrel shifter (32 bits/clock) to execute complicated instructions at high speeds. figure 1-1 shows the internal block diagram. figure 1-1. internal block diagram of v850e1 cpu data cache rom instruction queue multiplier (32 32 64) barrel shifter alu instruction cache program counter general register system register 22 user?s manual u14559ej2v0um chapter 2 register set the registers can be classified into two types: program registers that can be used for general programming, and system registers that can control the execution environment. all the registers are 32 bits wide. figure 2-1. registers (a) program registers 0 31 r0 (zero register) r1 (assembler-reserved register) r2 r3 (stack pointer (sp)) r4 (global pointer (gp)) r5 (text pointer (tp)) r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 r30 (element pointer (ep)) r31 (link pointer (lp)) pc (program counter) (b) system registers 0 31 eipc (interrupt status saving register) eipsw (interrupt status saving register) fepc (nmi status saving register) fepsw (nmi status saving register) ecr (exception cause register) psw (program status word) ctpc (callt caller status saving register) ctpsw (callt caller status saving register) dbpc (exception/debug trap status saving register) dbpsw (exception/debug trap status saving register) ctbp (callt base pointer) dir (debug interface register) bpc0 (breakpoint control register 0) asid (program id register) bpav0 (breakpoint address setting register 0) bpam1 (breakpoint address mask register 1) bpdv0 (breakpoint data setting register 0) bpdm1 (breakpoint data mask register 1) bpc1 (breakpoint control register 1) bpav1 (breakpoint address setting register 1) bpam0 (breakpoint address mask register 0) bpdv1 (breakpoint data setting register 1) bpdm0 (breakpoint data mask register 0) note these registers are reserved for debug function. only the NU85E and NU85Et can be used. the nb85e, nb85et, v850e/ma1, v850e/ma2, v850e/ia1, and v850e/ia2 cannot be used. note chapter 2 register set 23 user?s manual u14559ej2v0um 2.1 program registers there are general registers (r0 to r31) and program counter (pc) in the program registers. table 2-1. program registers program register name function description r0 zero register always holds 0. r1 assembler-reserved register used as working register for address generation. r2 address/data variable register (when the real-time os to be used is not using r2) r3 stack pointer (sp) used for stack frame generation when function is called. r4 global pointer (gp) used to access global variable in data area. r5 text pointer (tp) used as register for pointing start address of text area (area where program code is placed) r6 to r29 address/data variable registers r30 element pointer (ep) used as base pointer for address generation when memory is accessed. general register r31 link pointer (lp) used when compiler calls function. program counter pc holds instruction address during program execution. remark for detailed descriptions of r1, r3, r4, r5, and r31 used by assembler and c compiler, refer to the ca850 (c compiler package) user?s manual assembly language . (1) general registers (r0 to r31) thirty-two general registers, r0 to r31, are provided. all these registers can be used for data variable or address variable. however, r0 and r30 are implicitly used by instructions, and care must be exercised in using these registers. r0 is a register that always holds 0, and is used for operations and offset 0 addressing. r30 is used as a base pointer when accessing memory using the sld and sst instructions. r1, r3, r4, r5, and r31 are implicitly used by the assembler and c compiler. before using these registers, therefore, their contents must be saved so that they are not lost. the contents must be restored to the registers after the registers have been used. r2 is sometimes used by the real-time os. when the real-time os to be used is not using r2, r2 can be used as a variable register. (2) program counter (pc) this register holds an instruction address during program execution. the lower 26 bits of this register are valid, and bits 31 to 26 are reserved for future function expansion (fixed to 0). if a carry occurs from bit 25 to bit 26, it is ignored. bit 0 is always fixed to 0, and execution cannot branch to an odd address. figure 2-2. program counter (pc) 31 26 25 1 0 pc 0 initial value 00000000h 000000 (instruction address during execution) chapter 2 register set 24 user?s manual u14559ej2v0um 2.2 system registers the system registers control the status and holds information on interrupts. system registers can be read or written by specifying the relevant system register number from the following list using the ldsr and stsr instructions. table 2-2. system register numbers operand specifiability register no. register name ldsr instruction stsr instruction 0 interrupt status saving register (eipc) { { 1 interrupt status saving register (eipsw) { { 2 nmi status saving register (fepc) { { 3 nmi status saving register (fepsw) { { 4 exception cause register (ecr) { 5 program status word (psw) { { 6 to 15 (numbers reserved for future function expansion (operation cannot be guaranteed if accessed)) 16 callt caller status saving register (ctpc) { { 17 callt caller status saving register (ctpsw) { { 18 exception/debug trap status saving register (dbpc) { note 1 { 19 exception/debug trap status saving register (dbpsw) { note 1 { 20 callt base pointer (ctbp) { { 21 debug interface register (dir) { note 1 { note 1 22 breakpoint control registers 0 and 1 (bpc0, bpc1) note 2 { note 1 { note 1 23 program id register (asid) { { 24 breakpoint address setting registers 0 and 1 (bpav0, bpav1) note 2 { note 1 { note 1 25 breakpoint address mask registers 0 and 1 (bpam0, bpam1) note 2 { note 1 { note 1 26 breakpoint data setting registers 0 and 1 (bpdv0, bpdv1) note 2 { note 1 { note 1 27 breakpoint data mask registers 0 and 1 (bpdm0, bpdm1) note 2 { note 1 { note 1 28 to 31 (numbers reserved for future function expansion (operation cannot be guaranteed if accessed)) notes 1. these registers can be accessed only in debug mode of the NU85E and NU85Et. accessing to these registers of the nb85e, nb85et, v850e/ma1, v850e/ma2, v850e/ia1, and v850e/ia2 is prohibited. if they are accessed, the operation is not guaranteed. 2. the actual register to be accessed is specified by the cs bit of the dir register. caution when returning using the reti instruction after setting bit 0 of eipc, fepc, or ctpc to 1 using the ldsr instruction, the value of bit 0 is ignored (because bit 0 of the pc is fixed to 0). therefore, be sure to set an even number (bit 0 = 0) when setting a value in eipc, fepc, or ctpc. remark o: accessible : inaccessible chapter 2 register set 25 user?s manual u14559ej2v0um 2.2.1 interrupt status saving registers (eipc, eipsw) two interrupt status saving registers are provided: eipc and eipsw. if a software exception or maskable interrupt occurs, the contents of the program counter (pc) are saved to eipc, and the contents of the program status word (psw) are saved to eipsw (if a non-maskable interrupt (nmi) occurs, the contents are saved to nmi status saving registers (fepc, fepsw)). except for part of instructions, the address of the instruction next to the one executed when the software exception or maskable interrupt has occurred is saved to the eipc (see table 6-1 interrupt/exception codes ). the current value of the psw is saved to the eipsw. because only one pair of interrupt status saving registers is provided, the contents of these registers must be saved by program when multiple interrupts are enabled. bits 31 to 26 of the eipc and bits 31 to 12, 10 to 8 of the eipsw are reserved for future function expansion (fixed to 0). figure 2-3. interrupt status saving registers (eipc, eipsw) 31 0 eipsw (contents of psw) 8 11 31 26 25 0 eipc (contents of pc) 000000 000000 000000 000000 0 0 00 note 9 10 12 initial value 0xxxxxxxh (x: undefined) initial value 00000xxxh 0 (x: undefined) note contents of ss flag in psw chapter 2 register set 26 user?s manual u14559ej2v0um 2.2.2 nmi status saving registers (fepc, fepsw) two nmi status saving registers are provided: fepc and fepsw. if a non-maskable interrupt (nmi) occurs, the contents of the program counter (pc) are saved to fepc, and the contents of the program status word (psw) are saved to fepsw. except for part of instructions, the address of the instruction next to the one executed when the nmi has occurred is saved to the fepc (see table 6-1 interrupt/exception codes ). the current value of the psw is saved to the fepsw. because only one pair of nmi status saving registers is provided, the contents of these registers must be saved by program when multiple interrupts are enabled. bits 31 to 26 of the fepc and bits 31 to 12, 10 to 8 of the fepsw are reserved for future function expansion (fixed to 0). figure 2-4. nmi status saving registers (fepc, fepsw) 31 26 25 0 fepc (contents of pc) 31 0 fepsw (contents of psw) 000000 000000 000000 00000 0 0 8 11 0 00 note 9 10 12 initial value 0xxxxxxxh (x: undefined) 00000xxxh 0 (x: undefined) initial value note contents of ss flag in psw 2.2.3 exception cause register (ecr) the exception cause register (ecr) holds the cause information when an exception or interrupt occurs. the ecr holds an exception code which identifies each interrupt source (see table 6-1 interrupt/exception codes ). this is a read-only register, and therefore, no data can be written to it by using the ldsr instruction. figure 2-5. exception cause register (ecr) 31 0 ecr fecc eicc 16 15 initial value 00000000h bit position bit name function 31 to 16 fecc exception code of non-maskable interrupt (nmi) 15 to 0 eicc exception code of exception or maskable interrupt chapter 2 register set 27 user?s manual u14559ej2v0um 2.2.4 program status word (psw) the program status word (psw) is a collection of flags that indicate the status of the program (result of instruction execution) and the status of the cpu. if the contents of the bits in this register are modified by the ldsr instruction, the psw will assume the new value immediately after the ldsr instruction has been executed. in setting the id flag to 1, however, interrupt requests are already disabled even while the ldsr instruction is executing. bits 31 to 12, 10 to 8 are reserved for future function expansion (fixed to 0). figure 2-6. program status word (psw) (1/2) 31 87 6 5 4 3 2 1 0 psw n p s a t e p i d o v sz c y initial value 00000020h 000000 000000 000000 0 0 000 11 s s 9 10 12 bit position flag name function 11 ss note 1 operates with single-step execution when this flag is set to 1 (debug trap occurs each time instruction is executed). this flag is cleared to 0 when branching to the interrupt servicing routine. when the se bit of dir register is 0, this flag is not set (fixed to 0). 7np indicates that non-maskable interrupt (nmi) processing is in progress. this flag is set to 1 when nmi request is acknowledged, and multiple interrupts are disabled. 0: nmi processing is not in progress 1: nmi processing is in progress 6ep indicates that exception processing is in progress. this flag is set to 1 when an exception occurs. even when this bit is set, interrupt requests can be acknowledged. 0: exception processing is not in progress 1: exception processing is in progress 5id indicates whether maskable interrupt request can be acknowledged. 0: interrupt can be acknowledged 1: interrupt cannot be acknowledged 4 sat note 2 indicates that an overflow has occurred in a saturate operation and the result is saturated. this is a cumulative flag. when the result is saturated, the flag is set to 1 and is not cleared to 0 even if the next result does not saturate. to clear this flag to 0, use the ldsr instruction. this flag is neither set to 1 nor cleared to 0 by execution of arithmetic operation instruction. 0: not saturated 1: saturated 3cy indicates whether carry or borrow occurred as a result of the operation. 0: carry or borrow did not occur 1: carry or borrow occurred 2 ov note 2 indicates whether overflow occurred as a result of the operation. 0: overflow did not occur 1: overflow occurred remark see the following page for an explanation of the note 2. note 1. only the NU85E and NU85Et can be used. the nb85e, nb85et, v850e/ma1, v850e/ma2, v850e/ia1, and v850e/ia2 cannot be used. chapter 2 register set 28 user?s manual u14559ej2v0um figure 2-6. program status word (psw) (2/2) 31 87 6 5 4 3 2 1 0 psw n p s a t e p i d o v sz c y initial value 00000020h 000000 000000 000000 0 0 000 11 s s 9 10 12 bit position flag name function 1 s note 2 indicates whether the result of the operation is negative. 0: result is positive or zero 1: result is negative 0z indicates whether the result of the operation is zero. 0: result is not zero 1: result is zero note 2. in the case of saturate instructions, the sat, s, and ov flags will be set according to the result of the operation as shown in the table below. note that the sat flag is set to 1 only when the ov flag has been set to 1 during saturate operation. status of flag status of operation result sat ov s operation result of saturation processing maximum positive value is exceeded 1 1 0 7fffffffh maximum negative value is exceeded 1 1 1 80000000h positive (not exceeding maximum value) holds the value before 0 0 operation result negative (not exceeding maximum value) operation 1 2.2.5 callt caller status saving registers (ctpc, ctpsw) two callt caller status saving registers are provided: ctpc and ctpsw. if a callt instruction is executed, the contents of the program counter (pc) are saved to ctpc, and the contents of the program status word (psw) are saved to ctpsw. the contents saved to the ctpc are the address of the instruction next to the callt instruction. the current value of the psw is saved to the ctpsw. bits 31 to 26 of the ctpc and bits 31 to 12, 10 to 8 of the ctpsw are reserved for future function expansion (fixed to 0). chapter 2 register set 29 user?s manual u14559ej2v0um figure 2-7. callt caller status saving registers (ctpc, ctpsw) 31 26 25 0 ctpc (contents of pc) 31 0 ctpsw (contents of psw) 000000 000000 000000 000000 0 0 8 11 00 note 9 10 12 initial value 0xxxxxxxh (x: undefined) 00000xxxh 0 initial value (x: undefined) note contents of ss flag in psw 2.2.6 exception/debug trap status saving registers (dbpc, dbpsw) two exception/debug trap status saving registers are provided: dbpc and dbpsw. if an exception trap or debug trap note occurs, the contents of the program counter (pc) are saved to dbpc, and the contents of the program status word (psw) are saved to dbpsw. the contents saved to the dbpc are the address of the instruction next to the one executed when the exception trap or debug trap has occurred. the current value of the psw is saved to the dbpsw. bits 31 to 26 of the dbpc and bits 31 to 12, 10 to 8 of the dbpsw are reserved for future function expansion (fixed to 0). note the nb85e and nb85et do not support debug trap. figure 2-8. exception/debug trap status saving registers (dbpc, dbpsw) 31 26 25 0 dbpc (contents of pc) 31 dbpsw 000000 000000 000000 00000 0 0 0 (contents of psw) 0 8 11 00 note 9 10 12 initial value 0xxxxxxxh (x: undefined) 00000xxxh 0 initial value (x: undefined) note contents of ss flag in psw chapter 2 register set 30 user?s manual u14559ej2v0um 2.2.7 callt base pointer (ctbp) the callt base pointer (ctbp) is used to specify a table address and to generate a target address (bit 0 is fixed to 0). bits 31 to 26 are reserved for future function expansion (fixed to 0). figure 2-9. callt base pointer (ctbp) 31 26 25 0 ctbp (base address) 000000 0 initial value 0xxxxxxxh (x: undefined) 2.2.8 debug interface register (dir) the debug interface register (dir) indicates the control and status of the debug function. the values of the bits in this register can be changed by using the ldsr instruction. changed values become valid immediately after execution of this instruction. this register can only be set in the debug mode (dm bit = 1). bits 14 to 8, 6 to 4, 2, and 1 are undefined in the user mode (dm bit = 0). bits 31 to 15 and 7 are reserved for future function expansion (fixed to 0). caution use of the debug interface register (dir) is possible only for the NU85E or NU85Et, not for the nb85e, nb85et, v850e/ma1, v850e/ma2, v850e/ia1, or v850e/ia2. figure 2-10. debug interface register (dir) (1/2) 31 87 3 2 1 0 dir a t d m initial value 00000040h 000000 000000 000 s q r e c s 0 0 s e 11 9 10 c e m a a e 0 m t i n t 1 t 0 c m 4 5 6 12 13 14 15 bit position bit name function 14 sq sets sequential break mode. 0: normal break mode 1: sequential break mode 13 re sets range break mode. 0: normal break mode 1: range break mode 12 cs sets break register bank. 0: bank 0 register (channel 0 control register) selected 1: bank 1 register (channel 1 control register) selected 11 ce enables/disables combo interrupt. 0: combo interrupt disabled 1: combo interrupt enabled 10 ma enables/disables misalign access exception detection. 0: misalign access exception detection disabled 1: misalign access exception detection enabled chapter 2 register set 31 user?s manual u14559ej2v0um figure 2-10. debug interface register (dir) (2/2) bit position bit name function 9 ae enables/disables alignment error exception detection. 0: alignment error exception detection disabled 1: alignment error exception detection enabled 8 se enables/disables writing to ss flag of psw. 0: writing to ss flag disabled (ss flag is fixed to 0) 1: writing to ss flag enabled 6 in note 1 set to 1 by break register reset. 5 t1 note 1 set to 1 by channel 1 break generation. 4 t0 note 1 set to 1 by channel 0 break generation. 3 cm note 2 set to 1 by shift to combo interrupt routine or debug monitor routine 2. 2 mt note 1 set to 1 by detection of misalign access exception. 1 at note 1 set to 1 by detection of alignment error exception. 0 dm note 2 set to 1 by shift to debug mode. notes 1. can only be cleared to 0 by ldsr instruction. 2. the dm and cm bits change as shown below. 0 1 0 1 0 1 0 0 1 0 main routine debug monitor routine 1 combo interrupt routine debug monitor routine 2 dm bit cm bit user mode debug mode user mode debug mode user mode debug mode user mode debug trap maskable/ non-maskable interrupt debug t rap chapter 2 register set 32 user?s manual u14559ej2v0um 2.2.9 breakpoint control registers 0 and 1 (bpc0, bpc1) breakpoint control registers 0 and 1 (bpc0, bpc1) indicate the control and status of the debug function. one or other of these registers is enabled by the setting of the cs bit of dir register. the values of the bits in these registers can be changed by using the ldsr instruction. changed values become valid immediately after execution of this instruction. these registers can only be set in the debug mode (dm bit = 1). in the user mode, bit 0 = 0, and bits 23 to 15, 11 to 7, and 4 to 1 are undefined. bits 31 to 24, 14 to 12, 6, and 5 are reserved for future function expansion (fixed to 0). caution use of breakpoint control registers 0 and 1 (bpc0, bpc1) is possible only for the NU85E or NU85Et, not for the nb85e, nb85et, v850e/ma1, v850e/ma2, v850e/ia1, or v850e/ia2. figure 2-11. breakpoint control registers 0 and 1 (bpc0, bpc1) (1/2) 31 87 3 2 1 0 bpc0 w e r e initial value 00xxxxx0h 000000 0 0 0 v a 11 9 10 ty v d m d f e 12 13 14 15 0 0 6 0 0 i e 16 23 24 bp asid 31 87 3 2 1 0 bpc1 w e r e 00xxxxx0h 000000 0 0 0 v a 11 9 10 ty v d m d f e 12 13 14 15 0 0 6 0 0 i e 16 23 24 bp asid (x: undefined) initial value (x: undefined) 54 54 b e t e b e t e bit position bit name function 23 to 16 bp asid sets the program id that generates a break (valid only when ie bit = 1). 15 ie sets the comparison of the bp asid bit and the program id set in the asid register. 0: not compared 1: compared 11, 10 ty sets the type of access for which a break is detected. 0,0: access by all data types 0,1: byte access (including bit manipulation) 1,0: half-word access 1,1: word access note that the contents set in this register are ignored in the case of an instruction fetch. 9 vd sets the match condition of the data comparator. 0: break on a match 1: break on a mismatch 8 va sets the match condition of the address comparator. 0: break on a match 1: break on a mismatch 7 md sets the operation of the data comparator. if this bit is set to 1, the latency of access break is delay by 1 clock because even an data access break occurs before execution. 0: break on match of data and condition. 1: whether data coincides (data comparator) is ignored regardless of setting of vd bit or bpdvx and bpdmx registers chapter 2 register set 33 user?s manual u14559ej2v0um figure 2-11. breakpoint control registers 0 and 1 (bpc0, bpc1) (2/2) bit position bit name function 4 te note enables/disables trigger output. 0: trigger output disabled 1: trigger output enabled (outputs corresponding trigger before break occurs in channel 0 or 1). 3 be note sets whether or not a break in channel 0 or 1 is reported to cpu. 0: not reported. 1: reported (break). 2 fe enables/disables break on instruction fetch. 0: break disabled 1: break enabled 1 we enables/disables break on data write. 0: break disabled 1: break enabled 0 re enables/disables break on data read. 0: break disabled 1: break enabled note use of te and be bits is possible only for the NU85Et. 2.2.10 program id register (asid) this register sets the id of the program currently under execution. bits 31 to 8 are reserved for future function expansion (fixed to 0). caution use of the program id register (asid) is possible only for the NU85E or NU85Et, not for the nb85e, nb85et, v850e/ma1, v850e/ma2, v850e/ia1, or v850e/ia2. figure 2-12. program id register (asid) 31 87 0 asid 000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000 asid initial value 000000xxh (x: undefined) bit position flag name function 7 to 0 asid id of program currently under execution chapter 2 register set 34 user?s manual u14559ej2v0um 2.2.11 breakpoint address setting registers 0 and 1 (bpav0, bpav1) these registers set the breakpoint addresses to be used by the address comparator. one or other of these registers is enabled by the setting of the cs bit of dir register. bits 31 to 28 are reserved for future function expansion (fixed to 0). caution use of breakpoint address setting registers 0 and 1 (bpav0, bpav1) is possible only for the NU85E or NU85Et, not for the nb85e, nb85et, v850e/ma1, v850e/ma2, v850e/ia1, or v850e/ia2. figure 2-13. breakpoint address setting registers 0 and 1 (bpav0, bpav1) 31 0 bpav0 0000 (breakpoint address) 27 28 initial value 0xxxxxxxh (x: undefined) 31 0 bpav1 0000 27 28 0xxxxxxxh (breakpoint address) initial value (x: undefined) 2.2.12 breakpoint address mask registers 0 and 1 (bpam0, bpam1) these registers set the bit mask for address comparison (masked by 1). one or other of these registers is enabled by the setting of the cs bit of dir register. bits 31 to 28 are reserved for future function expansion (fixed to 0). caution use of breakpoint address mask registers 0 and 1 (bpam0, bpam1) is possible only for the NU85E or NU85Et, not for the nb85e, nb85et, v850e/ma1, v850e/ma2, v850e/ia1, or v850e/ia2. figure 2-14. breakpoint address mask registers 0 and 1 (bpam0, bpam1) 31 0 bpam0 0000 (breakpoint address mask) 27 28 initial value 0xxxxxxxh (x: undefined) 31 0 bpam1 0000 27 28 0xxxxxxxh (breakpoint address mask) initial value (x: undefined) chapter 2 register set 35 user?s manual u14559ej2v0um 2.2.13 breakpoint data setting registers 0 and 1 (bpdv0, bpdv1) these registers set the breakpoint data to be used by the data comparator. one or other of these registers is enabled by the setting of the cs bit of dir register. caution use of breakpoint data setting registers 0 and 1 (bpdv0, bpdv1) is possible only for the NU85E or NU85Et, not for the nb85e, nb85et, v850e/ma1, v850e/ma2, v850e/ia1, or v850e/ia2. figure 2-15. breakpoint data setting registers 0 and 1 (bpdv0, bpdv1) 31 0 bpdv0 initial value undefined (breakpoint data) 31 0 bpdv1 (breakpoint data) initial value undefined 2.2.14 breakpoint data mask registers 0 and 1 (bpdm0, bpdm1) these registers set the bit mask for data comparison (masked by 1). one or other of these registers is enabled by the setting of the cs bit of dir register. caution use of breakpoint data mask registers 0 and 1 (bpdm0, bpdm1) is possible only for the NU85E or NU85Et, not for the nb85e, nb85et, v850e/ma1, v850e/ma2, v850e/ia1, or v850e/ia2. figure 2-16. breakpoint data mask registers 0 and 1 (bpdm0, bpdm1) 31 0 bpdm0 initial value undefined (breakpoint data mask) 31 0 bpdm1 (breakpoint data mask) initial value undefined 36 user?s manual u14559ej2v0um chapter 3 data type 3.1 data format the following data types are supported (see 3.2 data representation ). ? integer (32, 16, 8 bits) unsigned integer (32, 16, 8 bits) bit three types of data lengths: word (32 bits), half-word (16 bits), and byte (8 bits) are supported. byte 0 of any data is always the least significant byte (this is called little endian) and shown at the rightmost position in figures throughout this manual. the following paragraphs describe the data format where data of fixed length is in memory. (1) word a word is 4-byte (32-bit) contiguous data that starts from any word boundary note . each bit is assigned a number from 0 to 31. the lsb (least significant bit) is bit 0 and the msb (most significant bit) is bit 31. a word is specified by its address a (with the 2 lowest bits fixed to 0 when misalign access is disabled note ), and occupies 4 bytes, a, a+1, a+2, and a+3. note when misalign access is enabled, any byte boundary can be accessed whether access is in half- word or word units. see 3.3 data alignment . 31 24 23 16 15 7 0 data 8 address a a+1 a+2 a+3 l b s m b s chapter 3 data type 37 37 user?s manual u14559ej2v0um (2) half-word a half-word is 2-byte (16-bit) contiguous data that starts from any half-word boundary note . each bit is assigned a number from 0 to 15. the lsb is bit 0 and the msb is bit 15. a half-word is specified by its address a (with the lowest bit fixed to 0 note ), and occupies 2 bytes, a and a+1. note when misalign access is enabled, any byte boundary can be accessed whether access is in half- word or word units. see 3.3 data alignment . 15 7 0 data 8 address a a+1 m b s l b s (3) byte a byte is 8-bit contiguous data that starts from any byte boundary note . each bit is assigned a number from 0 to 7. the lsb is bit 0 and the msb is bit 7. a byte is specified by its address a. note when misalign access is enabled, any byte boundary can be accessed whether access is in half- word or word units. see 3.3 data alignment . 7 0 data address a l b s m b s (4) bit a bit is 1-bit data at the nth bit position in 8-bit data that starts from any byte boundary note . a bit is specified by its address a and bit number n. note when misalign access is enabled, any byte boundary can be accessed whether access is in half- word or word units. see 3.3 data alignment . 7 byte of address a ... 0 address a bit number n data chapter 3 data type 38 38 user?s manual u14559ej2v0um 3.2 data representation 3.2.1 integer an integer is expressed as a binary number of 2?s complement and is 32, 16, or 8 bits long. regardless of its length, the bit 0 of an integer is the least significant bit. the higher the bit number, the more significant the bit. because 2?s complement is used, the most significant bit is used as a sign bit. the integer range of each data length is as follows. ? word (32 bits): ?2,147,483,648 to +2,147,483,647 ? half-word (16 bits): ?32,768 to +32,767 ? byte (8 bits): ?128 to +127 3.2.2 unsigned integer while an integer is data that can take either a positive or a negative value, an unsigned integer is an integer that is not negative. like an integer, an unsigned integer is also expressed as 2?s complement and is 32, 16, or 8 bits long. regardless of its length, bit 0 of an unsigned integer is the least significant bit, and the higher the bit number, the more significant the bit. however, no sign bit is used. the unsigned integer range of each data length is as follows. ? word (32 bits): 0 to 4,294,967,295 ? half-word (16 bits): 0 to 65,535 ? byte (8 bits): 0 to 255 3.2.3 bit 1-bit data that can take a value of 0 (cleared) or 1 (set) can be handled as a bit data. bit manipulation can be performed only to 1-byte data in the memory space in the following four ways: ? set ? clear ? invert ? test chapter 3 data type 39 39 user?s manual u14559ej2v0um 3.3 data alignment data to be allocated in memory must be aligned at an appropriate boundary when misalign access is disabled. therefore, word data must be aligned at a word boundary (the lower 2 bits of the address are 0), and half-word data must be aligned at a half-word boundary (the lower 1 bit of the address is 0). if data is not aligned at a boundary and misalign access disabled, the data is accessed with the lowest bit(s) of the address (lower 2 bits in the case of word data and lowest 1 bit in the case of half-word data) automatically masked. this will cause loss of data and truncation of the least significant bytes. when misalign access is enabled, it is possible to place word or half-word data at any address, but if data is not aligned at a boundary, one or more bus cycles is generated, which lowers the bus efficiency. 40 user?s manual u14559ej2v0um chapter 4 address space the v850e1 cpu supports a 4 gb linear address space. both memory and i/o are mapped to this address space (memory-mapped i/o). the v850e1 cpu (nb85e) outputs 32-bit addresses to the memory and i/o. the maximum address is 2 32 ? 1. byte data allocated at each address is defined with bit 0 as lsb and bit 7 as msb. in regards to multiple-byte data, the byte with the lowest address value is defined to have the lsb and the byte with the highest address value is defined to have the msb (little endian). data consisting of 2 bytes is called a half-word, and 4-byte data is called a word. in this user ? s manual, data consisting of 2 or more bytes is illustrated as shown below, with the lower address shown on the right and the higher address on the left. 31 24 23 16 15 7 0 8 data address data address data address a a+1 a+2 a+3 15 7 0 8 a a+1 7 0 a word at address a ............................................................................................ half-word at address a ............................................................................................................................... ....... byte at address a ....... chapter 4 addr ess space 41 user ? s manual u14559ej2v0um 4.1 memory map the v850e1 cpu employs a 32-bit architecture and supports a linear address space (data area) of up to 4 gb for operand addressing (data access). it supports a linear address space (program area) of up to 64 mb for instruction addressing. figure 4-1 shows the memory map. figure 4-1. memory map (a) address space (b) program area 00000000h 03ffffffh 04000000h ffffffffh data area (4 gb linear) program area (64 mb linear) 3ffffffh 3fff000h 3ffefffh 0000000h 64 mb peripheral i/o area (4 kb) ram area external memory area rom area chapter 4 addr ess space 42 user ? s manual u14559ej2v0um 4.2 addressing mode the cpu generates two types of addresses: instruction addresses used for instruction fetch and branch operations; and operand addresses used for data access. 4.2.1 instruction address an instruction address is determined by the contents of the program counter (pc), and is automatically incremented (+2) according to the number of bytes of an instruction to be fetched each time an instruction has been executed. when a branch instruction is executed, the branch destination address is loaded into the pc using one of the following two addressing modes: (1) relative addressing (pc relative) the signed 9- or 22-bit data of an instruction code (displacement: disp ) is added to the value of the program counter (pc). at this time, the displacement is treated as 2 ? s complement data with bits 8 and 21 serving as sign bits (s). this addressing is used for jarl disp22, reg2, jr disp22, and bcond disp9 instructions. figure 4-2. relative addressing (1/2) (a) jarl disp22, reg2 instruction, jr disp22 instruction 31 25 0 0pc 00000 31 22 0 sign extension s + 21 0 disp22 memory to be manipulated 31 25 0 0pc 00000 26 26 0 0 chapter 4 addr ess space 43 user ? s manual u14559ej2v0um figure 4-2. relative addressing (2/2) (b) bcond disp9 instruction 31 25 0 0pc 00000 31 0 sign extension s + 0 disp9 memory to be manipulated 31 25 0 0pc 00000 26 26 8 9 0 0 (2) register addressing (register indirect) the contents of a general register (reg1) specified by an instruction are transferred to the program counter (pc). this addressing is applied to the jmp [reg1] instruction. figure 4-3. register addressing (jmp [reg1] instruction) 31 0 reg1 memory to be manipulated 31 25 0 0pc 00000 26 0 chapter 4 addr ess space 44 user?s manual u14559ej2v0um 4.2.2 operand address when an instruction is executed, the register or memory area to be accessed is specified in one of the following four addressing modes: (1) register addressing the general register or system register specified in the general register specification field is accessed as operand. this addressing mode applies to instructions using the operand format reg1, reg2, reg3, or regid. (2) immediate addressing the 5-bit or 16-bit data for manipulation is contained in the instruction code. this addressing mode applies to instructions using the operand format imm5, imm16, vector, or cccc. remark vector: operand that is 5-bit immediate data to specify trap vector (00h to 1fh), and is used in trap instruction. cccc: operand consisting of 4-bit data used in cmov, sasf, and setf instructions to specify condition code. assigned as part of instruction code as 5-bit immediate data by appending 1- bit 0 above highest bit. (3) based addressing the following two types of based addressing are supported: (a) type 1 the address of the data memory location to be accessed is determined by adding the value in the specified general register (reg1) to the 16-bit displacement value (disp16) contained in the instruction code. this addressing mode applies to instructions using the operand format disp16 [reg1]. figure 4-4. based addressing (type 1) 31 0 reg1 memory to be manipulated 31 0 sign extension disp16 + 15 16 chapter 4 addr ess space 45 user?s manual u14559ej2v0um (b) type 2 the address of the data memory location to be accessed is determined by adding the value in the element pointer (r30) to the 7- or 8-bit displacement value (disp7, disp8). this addressing mode applies to sld and sst instructions. figure 4-5. based addressing (type 2) 31 0 r30 (element pointer) memory to be manipulated 31 0 0 (zero extension) disp8 or disp7 + 7 8 remark byte access: disp7 half-word access and word access: disp8 (4) bit addressing this addressing is used to access 1 bit (specified with bit#3 of 3-bit data) among 1 byte of the memory space to be manipulated by using an operand address which is the sum of the contents of a general register (reg1) and a 16-bit displacement (disp16) sign-extended to a word length. this addressing mode applies only to bit manipulate instructions. figure 4-6. bit addressing 31 0 reg1 memory to be manipulated 31 0 sign extension disp16 + 15 16 n remark n: bit position specified with 3-bit data (bit#3) (n = 0 to 7) 46 user?s manual u14559ej2v0um chapter 5 instruction 5.1 instruction format there are two types of instruction formats: 16-bit and 32-bit. the 16-bit format instructions include binary operation, control, and conditional branch instructions, and the 32-bit format instructions include load/store, jump, and instructions that handle 16-bit immediate data. an instruction is actually stored in memory as follows: lower bytes of instruction (including bit 0) lower address higher bytes of instruction (including bit 15 or bit 31) higher address caution some instructions have an unused field (rfu). this field is reserved for future expansion and must be fixed to 0. (1) reg-reg instruction (format i) a 16-bit instruction format having a 6-bit opcode field and two general register specification fields. 15 11 10 5 4 0 reg2 opcode reg1 (2) imm-reg instruction (format ii) a 16-bit instruction format having a 6-bit opcode field, 5-bit immediate field, and a general register specification field. 15 11 10 5 4 0 reg2 opcode imm chapter 5 instruction 47 user ? s manual u14559ej2v0um (3) conditional branch instruction (format iii) a 16-bit instruction format having a 4-bit opcode field, 4-bit condition code field, and an 8-bit displacement field. 15 11 10 6 4 0 disp opcode cond disp 3 7 (4) 16-bit load/store instruction (format iv) a 16-bit instruction format having a 4-bit opcode field, a general register specification field, and a 7-bit displacement field (or 6-bit displacement field + 1-bit sub-opcode field). 15 11 10 6 0 reg2 opcode disp disp/sub-opcode 1 7 a 16-bit instruction format having a 7-bit opcode field, a general register specification field, and a 4-bit displacement field. 15 11 10 4 0 reg2 opcode disp 3 (5) jump instruction (format v) a 32-bit instruction format having a 5-bit opcode field, a general register specification field, and a 22-bit displacement field. 15 11 10 16 opcode disp 0 031 reg2 17 65 chapter 5 instruction 48 user ? s manual u14559ej2v0um (6) 3-operand instruction (format vi) a 32-bit instruction format having a 6-bit opcode field, two general register specification fields, and a 16-bit immediate field. 15 11 10 16 opcode imm 031 reg2 4 5 reg1 (7) 32-bit load/store instruction (format vii) a 32-bit instruction format having a 6-bit opcode field, two general register specification fields, and a 16-bit displacement field (or 15-bit displacement field + 1-bit sub-opcode field). 15 11 10 16 opcode disp 031 reg2 4 5 reg1 disp/sub-opcode 17 (8) bit manipulation instruction (format viii) a 32-bit instruction format having a 6-bit opcode field, 2-bit sub-opcode field, 3-bit bit specification field, a general register specification field, and a 16-bit displacement field. 15 11 10 16 opcode disp 031 bit # 4 5 reg1 sub 14 13 (9) extended instruction format 1 (format ix) a 32-bit instruction format having a 6-bit opcode field, 6-bit sub-opcode field, and two general register specification fields (one field may be register number field (regid) or condition code field (cond)). 15 11 10 16 17 opcode sub-opcode 031 reg2 4 5 reg1/regid/cond rfu rfu 27 26 20 21 0 chapter 5 instruction 49 user ? s manual u14559ej2v0um (10) extended instruction format 2 (format x) a 32-bit instruction format having a 6-bit opcode field and 6-bit sub-opcode field. 15 11 10 16 17 opcode sub-opcode 031 rfu 4 5 rfu rfu 27 26 20 21 13 12 rfu/sub-opcode rfu/imm/vector 0 (11) extended instruction format 3 (format xi) a 32-bit instruction format having a 6-bit opcode field, 6-bit and 1-bit sub-opcode field, and three general register specification fields. 15 11 10 16 opcode sub-opcode 031 reg2 4 5 rfu reg3 27 26 20 21 0 17 18 sub-opcode reg1 (12) extended instruction format 4 (format xii) a 32-bit instruction format having a 6-bit opcode field, 4-bit and 1-bit sub-opcode field, 10-bit immediate field, and two general register specification fields. 15 11 10 16 opcode sub-opcode 031 reg2 4 5 imm (high) reg3 27 26 22 0 17 18 imm (low) 23 sub-opcode (13) stack manipulation instruction 1 (format xiii) a 32-bit instruction format having a 5-bit opcode field, 5-bit immediate field, 12-bit register list field, and one general register specification field (or 5-bit sub-opcode field). 15 11 10 16 opcode reg2/sub-opcode 031 rfu 65 list 20 imm 121 chapter 5 instruction 50 user ? s manual u14559ej2v0um 5.2 outline of instructions (1) load instructions transfer data from memory to a register. the following instructions (mnemonics) are provided. (a) ld instructions ? ld.b: load byte ? ld.bu: load byte unsigned ? ld.h: load half-word ? ld.hu: load half-word unsigned ? ld.w: load word (b) sld instructions ? sld.b: short format load byte ? sld.bu: short format load byte unsigned ? sld.h: short format load half-word ? sld.hu: short format load half-word unsigned ? sld.w: short format load word (2) store instructions transfer data from register to a memory. the following instructions (mnemonics) are provided. (a) st instructions ? st.b: store byte ? st.h: store half-word ? st.w: store word (b) sst instructions ? sst.b: short format store byte ? sst.h: short format store half-word ? sst.w: short format store word (3) multiply instructions execute multiply processing in 1 to 2 clocks with on-chip hardware multiplier. the following instructions (mnemonics) are provided. ? mul: multiply word ? mulh: multiply half-word ? mulhi: multiply half-word immediate ? mulu: multiply word unsigned chapter 5 instruction 51 user ? s manual u14559ej2v0um (4) arithmetic operation instructions add, subtract, divide, transfer, or compare data between registers. the following instructions (mnemonics) are provided. ? add: add ? addi: add immediate ? cmov: conditional move ? cmp: compare ? div: divide word ? divh: divide half-word ? divhu: divide half-word unsigned ? divu: divide word unsigned ? mov: move ? movea: move effective address ? movhi: move high half-word ? sasf: shift and set flag condition ? setf: set flag condition ? sub: subtract ? subr: subtract reverse (5) saturated operation instructions execute saturation addition and subtraction. if the result of the operation exceeds the maximum positive value (7fffffffh), 7fffffffh is returned. if the result of the operation exceeds the maximum negative value (80000000h), 80000000h is returned. the following instructions (mnemonics) are provided. ? satadd: saturated add ? satsub: saturated subtract ? satsubi: saturated subtract immediate ? satsubr: saturated subtract reverse (6) logical operation instructions these instructions include logical operation and shift instructions. the shift instructions include arithmetic shift and logical shift instructions. operands can be shifted by two or more bit positions in one clock cycle by the on-chip barrel shifter. the following instructions (mnemonics) are provided. ? and: and ? andi: and immediate ? bsh: byte swap half-word ? bsw: byte swap word ? hsw: half-word swap word ? not: not ? or: or ? ori: or immediate ? sar: shift arithmetic right ? shl: shift logical left ? shr: shift logical right ? sxb: sign extend byte ? sxh: sign extend half-word chapter 5 instruction 52 user ? s manual u14559ej2v0um ? tst: test ? xor: exclusive or ? xori: exclusive or immediate ? zxb: zero extend byte ? zxh: zero extend half-word (7) branch instructions these instructions include unconditional branch instructions (jarl, jmp, jr) and conditional branch instruction (bcond) which alters the control depending on the status of flags. program control can be transferred to the address specified by a branch instruction. the following instructions (mnemonics) are provided. ? bcond (bc, be, bge, bgt, bh, bl, ble, blt, bn, bnc, bne, bnh, bnl, bnv, bnz, bp, br, bsa, bv, bz): branch on condition code ? jarl: jump and register link ? jmp: jump register ? jr: jump relative (8) bit manipulation instructions execute a logical operation to bit data in memory. only a specified bit is affected. the following instructions (mnemonics) are provided. ? clr1: clear bit ? not1: not bit ? set1: set bit ? tst1: test bit (9) special instructions these instructions are instructions not included in the categories of instructions described above. the following instructions (mnemonics) are provided. ? callt: call with table look up ? ctret: return from callt ? di: disable interrupt ? dispose: function dispose ? ei: enable interrupt ? halt: halt ? ldsr: load system register ? nop: no operation ? prepare: function prepare ? reti: return from trap or interrupt ? stsr: store system register ? switch: jump with table look up ? trap: trap chapter 5 instruction 53 user ? s manual u14559ej2v0um (10)debug function instructions these instructions are instructions reserved for debug function. the following instructions (mnemonics) are provided. ? dbret: return from debug trap ? dbtrap: debug trap caution the nb85e and nb85et do not support debug function instructions. chapter 5 instruction 54 user?s manual u14559ej2v0um 5.3 instruction set in this section, mnemonic of each instruction is described divided into the following items. ? instruction format: indicates the description and operand of the instruction (for symbols, see table 5-1 ). ? operation: indicates the function of the instruction (for symbols, see table 5-2 ). ? format: indicates the instruction format (see 5.1 instruction format ). ? opcode: indicates the bit field of the instruction opcode (for symbols, see table 5-3 ). ? flag: indicates the operation of the flag which is altered after executing the instruction. 0 indicates clear (reset), 1 indicates set, and ? indicates no change. ? explanation: explains the operation of the instruction. ? remark: explains the supplementary information of the instruction. ? caution: indicates the cautions. table 5-1. conventions of instruction format symbol meaning reg1 general register (used as source register) reg2 general register (mainly used as destination register. some are also used as source registers) reg3 general register (mainly used as remainder of division results or higher 32 bits of multiply results) bit#3 3-bit data for specifying bit number imm -bit immediate data disp -bit displacement data regid system register number vector 5-bit data for trap vector (00h to1fh) specification cccc 4-bit data for c ondition code specification sp stack pointer (r3) ep element pointer (r30) list lists of registers ( is a maximum number of registers) table 5-2. conventions of operation (1/2) symbol meaning assignment gr [ ] general register sr [ ] system register zero-extend (n) zero-extends n to word sign-extend (n) sign-extends n to word load-memory (a, b) reads data of size b from address a store-memory (a, b, c) writes data b of size c to address a load-memory-bit (a, b) reads bit b from address a store-memory-bit (a, b, c) writes c to bit b of address a chapter 5 instruction 55 user ? s manual u14559ej2v0um table 5-2. conventions of operation (2/2) symbol meaning saturated (n) performs saturation processing of n. if n > 7fffffffh as result of calculation, n = 7fffffffh. if n < 80000000h as result of calculation, n = 80000000h. result reflects result on flag byte byte (8 bits) half-word half-word (16 bits) word word (32 bits) +add ? subtract || bit concatenation multiply divide % remainder of division results and and or or xor exclusive or not logical negate logically shift left by logical left shift logically shift right by logical right shift arithmetically shift right by arithmetic right shift table 5-3. conventions of opcode symbol meaning r 1-bit data of code specifying reg1 or regid r 1-bit data of code specifying reg2 w 1-bit data of code specifying reg3 d 1-bit data of displacement i 1-bit data of immediate (indicates higher bits of immediate) i 1-bit data of immediate cccc 4-bit data for c ondition code specification cccc 4-bit data for condition code specification of bcond instruction bbb 3-bit data for bit number specification l 1-bit data of code specifying program register in register list chapter 5 instruction 56 user ? s manual u14559ej2v0um chapter 5 instruction 57 user ? s manual u14559ej2v0um chapter 5 instruction 58 user ? s manual u14559ej2v0um chapter 5 instruction 59 user ? s manual u14559ej2v0um chapter 5 instruction 60 user?s manual u14559ej2v0um chapter 5 instruction 61 user ? s manual u14559ej2v0um table 5-4. bcond instructions instruction condition code (cccc) status of flag branch condition bge 1110 (s xor ov) = 0 greater than or equal signed bgt 1111 ( (s xor ov) or z) = 0 greater than signed ble 0111 ( (s xor ov) or z) = 1 less than or equal signed signed integer blt 0110 (s xor ov) = 1 less than signed bh 1011 (cy or z) = 0 higher (greater than) bl 0001 cy = 1 lower (less than) bnh 0011 (cy or z) = 1 not higher (less than or equal) unsigned integer bnl 1001 cy = 0 not lower (greater than or equal) be 0010 z = 1 equal common bne 1010 z = 0 not equal bc 0001 cy = 1 carry bn 0100 s = 1 negative bnc 1001 cy = 0 no carry bnv 1000 ov = 0 no overflow bnz 1010 z = 0 not zero bp 1100 s = 0 positive br 0101 ? always (unconditional) bsa 1101 sat = 1 saturated bv 0000 ov = 1 overflow others bz 0010 z = 1 zero caution if executing a conditional branch instruction of a signed integer (bge, bgt, ble, or blt) when the sat flag is set to 1 as a result of executing a saturated operation instruction, the branch condition loses its meaning. in ordinary operations, if an overflow occurs, the s flag is inverted (0 1 or 1 0). this is because the result is a negative value if it exceeds the maximum positive value and it is a positive value if it exceeds the maximum negative value. however, when a saturated operation instruction is executed, and if the result exceeds the maximum positive value, the result is saturated with a positive value; if the result exceeds the maximum negative value, the result is saturated with a negative value. unlike the ordinary operation, therefore, the s flag is not inverted even if an overflow occurs. hence, the s flag is affected differently when the instruction is a saturate operation, as opposed to an ordinary operation. a branch condition which is an xor of s and ov flags will therefore have no meaning. chapter 5 instruction 62 user ? s manual u14559ej2v0um chapter 5 instruction 63 user ? s manual u14559ej2v0um chapter 5 instruction 64 user ? s manual u14559ej2v0um chapter 5 instruction 65 user ? s manual u14559ej2v0um chapter 5 instruction 66 user?s manual u14559ej2v0um chapter 5 instruction 67 user ? s manual u14559ej2v0um chapter 5 instruction 68 user?s manual u14559ej2v0um chapter 5 instruction 69 user ? s manual u14559ej2v0um chapter 5 instruction 70 user ? s manual u14559ej2v0um chapter 5 instruction 71 user ? s manual u14559ej2v0um chapter 5 instruction 72 user?s manual u14559ej2v0um chapter 5 instruction 73 user ? s manual u14559ej2v0um remark general registers in list12 are loaded in the downward direction. (r31, r30, ... r20) the 5-bit immediate imm5 is used to restore a stack frame for auto variables and temporary data. the lower 2-bit of address specified by sp is always masked to 0 even if misaligned access is enabled. if an interrupt occurs before updating the sp, execution is aborted, and the interrupt is processed. upon returning from the interrupt, the execution is restarted from the beginning, with the return address being the address of this instruction (sp will retain their original values prior to the start of execution). caution if an interrupt is generated during instruction execution, due to manipulation of the stack, the execution of that instruction may stop after the read/write cycle and register value rewriting are complete. execution is resumed after returning from the interrupt. chapter 5 instruction 74 user ? s manual u14559ej2v0um chapter 5 instruction 75 user?s manual u14559ej2v0um chapter 5 instruction 76 user ? s manual u14559ej2v0um (2) overflow occurs when the maximum negative value (80000000h) is divided by ? 1 (in which case the quotient is 80000000h) and when data is divided by 0 (in which case the quotient is undefined). if an interrupt occurs while this instruction is executed, execution is aborted, and the interrupt is processed. upon returning from the interrupt, the execution is restarted from the beginning, with the return address being the address of this instruction. also, general registers reg1 and reg2 will retain their original values prior to the start of execution. the higher 16 bits of general register reg1 are ignored when division is executed. if the address of reg2 is the same as the address of reg3, the remainder is stored to reg2 (= reg3). chapter 5 instruction 77 user ? s manual u14559ej2v0um chapter 5 instruction 78 user ? s manual u14559ej2v0um chapter 5 instruction 79 user ? s manual u14559ej2v0um chapter 5 instruction 80 user?s manual u14559ej2v0um chapter 5 instruction 81 user ? s manual u14559ej2v0um chapter 5 instruction 82 user ? s manual u14559ej2v0um chapter 5 instruction 83 user ? s manual u14559ej2v0um chapter 5 instruction 84 user ? s manual u14559ej2v0um chapter 5 instruction 85 user ? s manual u14559ej2v0um chapter 5 instruction 86 user ? s manual u14559ej2v0um remark if an interrupt occurs during instruction execution, execution is aborted, and the interrupt is processed. upon returning from the interrupt, the execution is restarted from the beginning, with the return address being the address of this instruction. [for v850e/ma1, v850e/ma2, v850e/ia1, or v850e/ia2] depending on the resource to be accessed (internal rom, internal ram, on-chip peripheral i/o, external memory), the bus cycle may be switched (this will not occur if the same resource is accessed). [for nb85e, nb85et, NU85E, NU85Et] the bus cycle sequence for accessing the different resources connected to each bus (vfb, vdb, vsb, npb, instruction cache bus, data cache bus) may be switched (this will not occur if the same bus is accessed). chapter 5 instruction 87 user ? s manual u14559ej2v0um chapter 5 instruction 88 user ? s manual u14559ej2v0um remark if an interrupt occurs during instruction execution, execution is aborted, and the interrupt is processed. upon returning from the interrupt, the execution is restarted from the beginning, with the return address being the address of this instruction. [for v850e/ma1, v850e/ma2, v850e/ia1, or v850e/ia2] depending on the resource to be accessed (internal rom, internal ram, on-chip peripheral i/o, external memory), the bus cycle may be switched (this will not occur if the same resource is accessed). [for nb85e, nb85et, NU85E, or NU85Et] the bus cycle sequence for accessing the different resources connected to each bus (vfb, vdb, vsb, npb, instruction cache bus, data cache bus) may be switched (this will not occur if the same bus is accessed). chapter 5 instruction 89 user ? s manual u14559ej2v0um chapter 5 instruction 90 user ? s manual u14559ej2v0um remark if an interrupt occurs during instruction execution, execution is aborted, and the interrupt is processed. upon returning from the interrupt, the execution is restarted from the beginning, with the return address being the address of this instruction. [for v850e/ma1, v850e/ma2, v850e/ia1, or v850e/ia2] depending on the resource to be accessed (internal rom, internal ram, on-chip peripheral i/o, external memory), the bus cycle may be switched (this will not occur if the same resource is accessed). [for nb85e, nb85et, NU85E, or NU85Et] the bus cycle sequence for accessing the different resources connected to each bus (vfb, vdb, vsb, npb, instruction cache bus, data cache bus) may be switched (this will not occur if the same bus is accessed). chapter 5 instruction 91 user ? s manual u14559ej2v0um chapter 5 instruction 92 user ? s manual u14559ej2v0um remark if an interrupt occurs during instruction execution, execution is aborted, and the interrupt is processed. upon returning from the interrupt, the execution is restarted from the beginning, with the return address being the address of this instruction. [for v850e/ma1, v850e/ma2, v850e/ia1, or v850e/ia2] depending on the resource to be accessed (internal rom, internal ram, on-chip peripheral i/o, external memory), the bus cycle may be switched (this will not occur if the same resource is accessed). [for nb85e, nb85et, NU85E, or NU85Et] the bus cycle sequence for accessing the different resources connected to each bus (vfb, vdb, vsb, npb, instruction cache bus, data cache bus) may be switched (this will not occur if the same bus is accessed). chapter 5 instruction 93 user ? s manual u14559ej2v0um chapter 5 instruction 94 user ? s manual u14559ej2v0um remark if an interrupt occurs during instruction execution, execution is aborted, and the interrupt is processed. upon returning from the interrupt, the execution is restarted from the beginning, with the return address being the address of this instruction. [for v850e/ma1, v850e/ma2, v850e/ia1, or v850e/ia2] depending on the resource to be accessed (internal rom, internal ram, on-chip peripheral i/o, external memory), the bus cycle may be switched (this will not occur if the same resource is accessed). [for nb85e, nb85et, NU85E, or NU85Et] the bus cycle sequence for accessing the different resources connected to each bus (vfb, vdb, vsb, npb, instruction cache bus, data cache bus) may be switched (this will not occur if the same bus is accessed). chapter 5 instruction 95 user?s manual u14559ej2v0um chapter 5 instruction 96 user?s manual u14559ej2v0um chapter 5 instruction 97 user ? s manual u14559ej2v0um chapter 5 instruction 98 user?s manual u14559ej2v0um chapter 5 instruction 99 user?s manual u14559ej2v0um chapter 5 instruction 100 user?s manual u14559ej2v0um chapter 5 instruction 101 user ? s manual u14559ej2v0um chapter 5 instruction 102 user?s manual u14559ej2v0um chapter 5 instruction 103 user?s manual u14559ej2v0um chapter 5 instruction 104 user?s manual u14559ej2v0um chapter 5 instruction 105 user?s manual u14559ej2v0um chapter 5 instruction 106 user?s manual u14559ej2v0um chapter 5 instruction 107 user?s manual u14559ej2v0um chapter 5 instruction 108 user?s manual u14559ej2v0um chapter 5 instruction 109 user?s manual u14559ej2v0um explanation (1) push (subtract 4 from sp and store the data to that address) general registers listed in list12. then subtract the data of 5-bit immediate imm5, logically shifted left by 2 and zero- extended to word length, from sp. (2) push (subtract 4 from sp and store the data to that address) general registers listed in list12. then subtract the data of 5-bit immediate imm5, logically shifted left by 2 and zero- extended to word length, from sp. next, load the data specified by 3rd operand (sp/imm) to ep. remark general registers in list12 is stored on the upward direction. (r20, r21, ... r31) the 5-bit immediate imm5 is used to make a stack frame for auto variables and temporary data. the lower 2 bits of the address specified by sp are always masked to 0 even if misaligned access is enabled. if an interrupt occurs before updating the sp, execution is aborted, and the interrupt is processed. upon returning from the interrupt, the execution is restarted from the beginning, with the return address being the address of this instruction (sp and ep will retain their original values prior to the start of execution). caution if an interrupt is generated during instruction execution, due to manipulation of the stack, the execution of that instruction may stop after the read/write cycle and register value rewriting are complete. chapter 5 instruction 110 user?s manual u14559ej2v0um chapter 5 instruction 111 user?s manual u14559ej2v0um caution when returning from a non-maskable interrupt or software exception routine using the reti instruction, the np and ep flags of psw must be set accordingly to restore the pc and psw: when returning from non-maskable interrupt routine using the reti instruction: np = 1 and ep = 0 when returning from a software exception routine using the reti instruction: ep = 1 use the ldsr instruction for setting the flags. interrupts are not accepted in the latter half of the id stage during ldsr execution because of the operation of the interrupt controller. chapter 5 instruction 112 user?s manual u14559ej2v0um chapter 5 instruction 113 user?s manual u14559ej2v0um chapter 5 instruction 114 user?s manual u14559ej2v0um chapter 5 instruction 115 user?s manual u14559ej2v0um chapter 5 instruction 116 user?s manual u14559ej2v0um chapter 5 instruction 117 user?s manual u14559ej2v0um chapter 5 instruction 118 user?s manual u14559ej2v0um chapter 5 instruction 119 user?s manual u14559ej2v0um chapter 5 instruction 120 user?s manual u14559ej2v0um table 5-5. condition codes condition code (cccc) condition name condition expression 0000 v ov = 1 1000 nv ov = 0 0001 c/l cy = 1 1001 nc/nl cy = 0 0010 z z = 1 1010 nz z = 0 0011 nh (cy or z) = 1 1011 h (cy or z) = 0 0100 s/n s = 1 1100 ns/p s = 0 0101 t always (unconditional) 1101 sa sat = 1 0110 lt (s xor ov) = 1 1110 ge (s xor ov) = 0 0111 le ((s xor ov) or z) = 1 1111 gt ((s xor ov) or z) = 0 chapter 5 instruction 121 user?s manual u14559ej2v0um chapter 5 instruction 122 user?s manual u14559ej2v0um chapter 5 instruction 123 user?s manual u14559ej2v0um chapter 5 instruction 124 user?s manual u14559ej2v0um caution the result of adding the element pointer and the 8-bit displacement zero-extended to word length can be of two types depending on the type of data to be accessed (half-word, word) and the misaligned mode setting. lower bits are masked to 0 and address is generated (when misaligned access is disabled) lower bits are not masked and address is generated (when misaligned access is enabled) (when misaligned access is enabled for the v850e/ma1, v850e/ma2, v850e/ia1, or v850e/ia2) for details on misaligned access, see 3.3 data alignment . also, if an interrupt is generated during instruction execution, the execution of that instruction may stop after the end of the read/write cycle. in this case, the instruction is re-executed after returning from the interrupt. therefore, except in cases when clearly no interrupt is generated, the ld instruction should be used for accessing i/o, fifo types, or other resources whose status is changed by the read cycle (the bus cycle is not re-executed even if an interrupt is generated while the ld or store instruction is being executed). chapter 5 instruction 125 user?s manual u14559ej2v0um chapter 5 instruction 126 user?s manual u14559ej2v0um caution the result of adding the element pointer and the 8-bit displacement zero-extended to word length can be of two types depending on the type of data to be accessed (half-word, word) and the misaligned mode setting. lower bits are masked to 0 and address is generated (when misaligned access is disabled) lower bits are not masked and address is generated (when misaligned access is enabled) (when misaligned access is enabled for the v850e/ma1, v850e/ma2, v850e/ia1, or v850e/ia2) for details on misaligned access, see 3.3 data alignment . also, if an interrupt is generated during instruction execution, the execution of that instruction may stop after the end of the read/write cycle. in this case, the instruction is re-executed after returning from the interrupt. therefore, except in cases when clearly no interrupt is generated, the ld instruction should be used for accessing i/o, fifo types, or other resources whose status is changed by the read cycle (the bus cycle is not re-executed even if an interrupt is generated while the ld or store instruction is being executed). chapter 5 instruction 127 user?s manual u14559ej2v0um chapter 5 instruction 128 user?s manual u14559ej2v0um caution the result of adding the element pointer and the 8-bit displacement zero-extended to word length can be of two types depending on the type of data to be accessed (half-word, word) and the misaligned mode setting. lower bits are masked to 0 and address is generated (when misaligned access is disabled) lower bits are not masked and address is generated (when misaligned access is enabled) (when misaligned access is enabled for the v850e/ma1, v850e/ma2, v850e/ia1, or v850e/ia2) for details on misaligned access, see 3.3 data alignment . also, if an interrupt is generated during instruction execution, the execution of that instruction may stop after the end of the read/write cycle. in this case, the instruction is re-executed after returning from the interrupt. therefore, except in cases when clearly no interrupt is generated, the ld instruction should be used for accessing i/o, fifo types, or other resources whose status is changed by the read cycle (the bus cycle is not re-executed even if an interrupt is generated while the ld or store instruction is being executed). chapter 5 instruction 129 user?s manual u14559ej2v0um chapter 5 instruction 130 user?s manual u14559ej2v0um caution the result of adding the element pointer and the 8-bit displacement zero-extended to word length can be of two types depending on the type of data to be accessed (half-word, word) and the misaligned mode setting. lower bits are masked to 0 and address is generated (when misaligned access is disabled) lower bits are not masked and address is generated (when misaligned access is enabled) (when misaligned access is enabled for the v850e/ma1, v850e/ma2, v850e/ia1, or v850e/ia2) for details on misaligned access, see 3.3 data alignment . also, if an interrupt is generated during instruction execution, the execution of that instruction may stop after the end of the read/write cycle. in this case, the instruction is re-executed after returning from the interrupt. therefore, except in cases when clearly no interrupt is generated, the ld instruction should be used for accessing i/o, fifo types, or other resources whose status is changed by the read cycle (the bus cycle is not re-executed even if an interrupt is generated while the ld or store instruction is being executed). chapter 5 instruction 131 user?s manual u14559ej2v0um chapter 5 instruction 132 user?s manual u14559ej2v0um caution the result of adding the element pointer and the 8-bit displacement zero-extended to word length can be of two types depending on the type of data to be accessed (half-word, word) and the misaligned mode setting. lower bits are masked to 0 and address is generated (when misaligned access is disabled) lower bits are not masked and address is generated (when misaligned access is enabled) (when misaligned access is enabled for the v850e/ma1, v850e/ma2, v850e/ia1, or v850e/ia2) for details on misaligned access, see 3.3 data alignment . also, if an interrupt is generated during instruction execution, the execution of that instruction may stop after the end of the read/write cycle. in this case, the instruction is re-executed after returning from the interrupt. therefore, except in cases when clearly no interrupt is generated, the ld instruction should be used for accessing i/o, fifo types, or other resources whose status is changed by the read cycle (the bus cycle is not re-executed even if an interrupt is generated while the ld or store instruction is being executed). chapter 5 instruction 133 user?s manual u14559ej2v0um chapter 5 instruction 134 user?s manual u14559ej2v0um remark if an interrupt occurs during instruction execution, execution is aborted, and the interrupt is processed. upon returning from the interrupt, the execution is restarted from the beginning, with the return address being the address of this instruction. [for v850e/ma1, v850e/ma2, v850e/ia1, or v850e/ia2] depending on the resource to be accessed (internal rom, internal ram, on-chip peripheral i/o, external memory), the bus cycle may be switched (this will not occur if the same resource is accessed). [for nb85e, nb85et, NU85E, or NU85Et] the bus cycle sequence for accessing the different resources connected to each bus (vfb, vdb, vsb, npb, instruction cache bus, data cache bus) may be switched (this will not occur if the same bus is accessed). chapter 5 instruction 135 user?s manual u14559ej2v0um chapter 5 instruction 136 user?s manual u14559ej2v0um remark if an interrupt occurs during instruction execution, execution is aborted, and the interrupt is processed. upon returning from the interrupt, the execution is restarted from the beginning, with the return address being the address of this instruction. [for v850e/ma1, v850e/ma2, v850e/ia1, or v850e/ia2] depending on the resource to be accessed (internal rom, internal ram, on-chip peripheral i/o, external memory), the bus cycle may be switched (this will not occur if the same resource is accessed). [for nb85e, nb85et, NU85E, or NU85Et] the bus cycle sequence for accessing the different resources connected to each bus (vfb, vdb, vsb, npb, instruction cache bus, data cache bus) may be switched (this will not occur if the same bus is accessed). chapter 5 instruction 137 user?s manual u14559ej2v0um chapter 5 instruction 138 user?s manual u14559ej2v0um remark if an interrupt occurs during instruction execution, execution is aborted, and the interrupt is processed. upon returning from the interrupt, the execution is restarted from the beginning, with the return address being the address of this instruction. [for v850e/ma1, v850e/ma2, v850e/ia1, or v850e/ia2] depending on the resource to be accessed (internal rom, internal ram, on-chip peripheral i/o, external memory), the bus cycle may be switched (this will not occur if the same resource is accessed). [for nb85e, nb85et, NU85E, or NU85Et] the bus cycle sequence for accessing the different resources connected to each bus (vfb, vdb, vsb, npb, instruction cache bus, data cache bus) may be switched (this will not occur if the same bus is accessed). chapter 5 instruction 139 user?s manual u14559ej2v0um chapter 5 instruction 140 user?s manual u14559ej2v0um remark if an interrupt occurs during instruction execution, execution is aborted, and the interrupt is processed. upon returning from the interrupt, the execution is restarted from the beginning, with the return address being the address of this instruction. [for v850e/ma1, v850e/ma2, v850e/ia1, or v850e/ia2] depending on the resource to be accessed (internal rom, internal ram, on-chip peripheral i/o, external memory), the bus cycle may be switched (this will not occur if the same resource is accessed). [for nb85e, nb85et, NU85E, or NU85Et] the bus cycle sequence for accessing the different resources connected to each bus (vfb, vdb, vsb, npb, instruction cache bus, data cache bus) may be switched (this will not occur if the same bus is accessed). chapter 5 instruction 141 user?s manual u14559ej2v0um chapter 5 instruction 142 user?s manual u14559ej2v0um remark if an interrupt occurs during instruction execution, execution is aborted, and the interrupt is processed. upon returning from the interrupt, the execution is restarted from the beginning, with the return address being the address of this instruction. [for v850e/ma1, v850e/ma2, v850e/ia1, or v850e/ia2] depending on the resource to be accessed (internal rom, internal ram, on-chip peripheral i/o, external memory), the bus cycle may be switched (this will not occur if the same resource is accessed). [for nb85e, nb85et, NU85E, or NU85Et] the bus cycle sequence for accessing the different resources connected to each bus (vfb, vdb, vsb, npb, instruction cache bus, data cache bus) may be switched (this will not occur if the same bus is accessed). chapter 5 instruction 143 user?s manual u14559ej2v0um chapter 5 instruction 144 user?s manual u14559ej2v0um remark if an interrupt occurs during instruction execution, execution is aborted, and the interrupt is processed. upon returning from the interrupt, the execution is restarted from the beginning, with the return address being the address of this instruction. [for v850e/ma1, v850e/ma2, v850e/ia1, or v850e/ia2] depending on the resource to be accessed (internal rom, internal ram, on-chip peripheral i/o, external memory), the bus cycle may be switched (this will not occur if the same resource is accessed). [for nb85e, nb85et, NU85E, or NU85Et] the bus cycle sequence for accessing the different resources connected to each bus (vfb, vdb, vsb, npb, instruction cache bus, data cache bus) may be switched (this will not occur if the same bus is accessed). chapter 5 instruction 145 user?s manual u14559ej2v0um chapter 5 instruction 146 user?s manual u14559ej2v0um chapter 5 instruction 147 user?s manual u14559ej2v0um chapter 5 instruction 148 user?s manual u14559ej2v0um chapter 5 instruction 149 user?s manual u14559ej2v0um chapter 5 instruction 150 user?s manual u14559ej2v0um chapter 5 instruction 151 user?s manual u14559ej2v0um chapter 5 instruction 152 user?s manual u14559ej2v0um chapter 5 instruction 153 user?s manual u14559ej2v0um chapter 5 instruction 154 user?s manual u14559ej2v0um chapter 5 instruction 155 user?s manual u14559ej2v0um chapter 5 instruction 156 user?s manual u14559ej2v0um chapter 5 instruction 157 user?s manual u14559ej2v0um chapter 5 instruction 158 user?s manual u14559ej2v0um 5.4 number of instruction execution clock cycles a list of the number of instruction execution clocks when the internal rom or internal ram is used is shown below. the number of instruction execution clock cycles differ depending on the combination of instructions. for details, see chapter 8 pipeline . the number of instruction execution clock cycles differ in the case of the nb85e, nb85et, NU85E, NU85Et and the v850e/ma1, v850e/ma2, v850e/ia1, v850e/ia2. table 5-6 shows the number of instruction execution clock cycles in the case of the nb85e, nb85et, NU85E, NU85Et and table 5-7 shows the case of the v850e/ma1, v850e/ma2, v850e/ia1, v850e/ia2. table 5-6. list of number of instruction execution clock cycles (nb85e, nb85et, NU85E, and NU85Et) (1/3) number of execution clocks type of instruction mnemonic operand byte irl ld.b disp16 [reg1] , reg2 4 1 1 note 1 ld.h disp16 [reg1] , reg2 4 1 1 note 1 ld.w disp16 [reg1] , reg2 4 1 1 note 1 ld.bu disp16 [reg1] , reg2 4 1 1 note 1 ld.hu disp16 [reg1] , reg2 4 1 1 note 1 sld.b disp7 [ep] , reg2 2 1 1 note 2 sld.bu disp4 [ep] , reg2 2 1 1 note 2 sld.h disp8 [ep] , reg2 2 1 1 note 2 sld.hu disp5 [ep] , reg2 2 1 1 note 2 load instructions sld.w disp8 [ep] , reg2 2 1 1 note 2 st.b reg2, disp16 [reg1] 4 1 1 1 st.h reg2, disp16 [reg1] 4 1 1 1 st.w reg2, disp16 [reg1] 4 1 1 1 sst.b reg2, disp7 [ep] 2 1 1 1 sst.h reg2, disp8 [ep] 2 1 1 1 store instructions sst.w reg2, disp8 [ep] 2 1 1 1 mul reg1, reg2, reg3 4 1 2 note 3 2 mul imm9, reg2, reg3 4 1 2 note 3 2 mulh reg1, reg2 2 1 1 2 mulh imm5, reg2 2 1 1 2 mulhi imm16, reg1, reg2 4 1 1 2 mulu reg1, reg2, reg3 4 1 2 note 3 2 multiply instructions mulu imm9, reg2, reg3 4 1 2 note 3 2 add reg1, reg2 2 1 1 1 add imm5, reg2 2 1 1 1 addi imm16, reg1, reg2 4 1 1 1 cmov cccc, r eg1, reg2, reg3 4 1 1 1 cmov cccc, imm5, r eg2, reg3 4 1 1 1 cmp reg1, reg2 2 1 1 1 arithmetic operation instructions cmp imm5, reg2 2 1 1 1 chapter 5 instruction 159 user?s manual u14559ej2v0um table 5-6. list of number of instruction execution clock cycles (nb85e, nb85et, NU85E, and NU85Et) (2/3) number of execution clocks type of instruction mnemonic operand byte irl div reg1, reg2, reg3 4 35 35 35 divh reg1, reg2 2 35 35 35 divh reg1, reg2, reg3 4 35 35 35 divhu reg1, reg2, reg3 4 34 34 34 divu reg1, reg2, reg3 4 34 34 34 mov reg1, reg2 2 1 1 1 mov imm5, reg2 2 1 1 1 mov imm32, reg1 6 2 2 2 movea imm16, reg1, reg2 4 1 1 1 movhi imm16, reg1, reg2 4 1 1 1 sasf cccc, reg2 4 1 1 1 setf cccc, reg2 4 1 1 1 sub reg1, reg2 2 1 1 1 arithmetic operation instructions subr reg1, reg2 2 1 1 1 satadd reg1, reg2 2 1 1 1 satadd imm5, reg2 2 1 1 1 satsub reg1, reg2 2 1 1 1 satsubi imm16, reg1, reg2 4 1 1 1 saturated operation instructions satsubr reg1, reg2 2 1 1 1 and reg1, reg2 2 1 1 1 andi imm16, reg1, reg2 4 1 1 1 bsh reg2, reg3 4 1 1 1 bsw reg2, reg3 4 1 1 1 hsw reg2, reg3 4 1 1 1 not reg1, reg2 2 1 1 1 or reg1, reg2 2 1 1 1 ori imm16, reg1, reg2 4 1 1 1 sar reg1, reg2 4 1 1 1 sar imm5, reg2 2 1 1 1 shl reg1, reg2 4 1 1 1 shl imm5, reg2 2 1 1 1 shr reg1, reg2 4 1 1 1 shr imm5, reg2 2 1 1 1 sxb reg1 2 1 1 1 sxh reg1 2 1 1 1 tst reg1, reg2 2 1 1 1 xor reg1, reg2 2 1 1 1 xori imm16, reg1, reg2 4 1 1 1 zxb reg1 2 1 1 1 logical operation instructions zxh reg1 2 1 1 1 chapter 5 instruction 160 user?s manual u14559ej2v0um table 5-6. list of number of instruction execution clock cycles (nb85e, nb85et, NU85E, and NU85Et) (3/3) number of execution clocks type of instruction mnemonic operand byte irl disp9 (when condition is satisfied) 2 2 note 4 2 note 4 2 note 4 bcond disp9 (when condition is not satisfied) 2 111 jarl disp22, reg2 4 2 2 2 jmp [reg1] 2 3 3 3 branch instructions jr disp22 4 2 2 2 clr1 bit#3, disp16 [reg1] 4 3 note 5 3 note 5 3 note 5 clr1 reg2, [reg1] 4 3 note 5 3 note 5 3 note 5 not1 bit#3, disp16 [reg1] 4 3 note 5 3 note 5 3 note 5 not1 reg2, [reg1] 4 3 note 5 3 note 5 3 note 5 set1 bit#3, disp16 [reg1] 4 3 note 5 3 note 5 3 note 5 set1 reg2, [reg1] 4 3 note 5 3 note 5 3 note 5 tst1 bit#3, disp16 [reg1] 4 3 note 5 3 note 5 3 note 5 bit manipulation instructions tst1 reg2, [reg1] 4 3 note 5 3 note 5 3 note 5 callt imm6 2 4 4 4 ctret ? 4 3 3 3 di ? 4 111 dispose imm5, list12 4 n+1 note 6 n+1 note 6 n+1 note 6 dispose imm5, list12, [reg1] 4 n+3 note 6 n+3 note 6 n+3 note 6 ei ? 4 111 halt ? 4 111 ldsr reg2, regid 4 1 1 1 nop ? 2 111 prepare list12, imm5 4 n+1 note 6 n+1 note 6 n+1 note 6 prepare list12, imm5, sp 4 n+2 note 6 n+2 note 6 n+2 note 6 prepare list12, imm5, imm16 6 n+2 note 6 n+2 note 6 n+2 note 6 prepare list12, imm5, imm32 8 n+3 note 6 n+3 note 6 n+3 note 6 reti ? 4 333 stsr regid, reg2 4 1 1 1 switch reg1 2 5 5 5 special instructions trap vector 4 3 3 3 dbret ? 4 3 3 3 debug function instructions note 7 dbtrap ? 2 333 undefined instruction code 4 3 3 3 chapter 5 instruction 161 user?s manual u14559ej2v0um notes 1. depends on the number of wait states (2 if no wait states). 2. depends on the number of wait states (1 if no wait states). 3. 1 clock shortened if reg2 = reg3 (lower 32 bits of results are not written to register) or reg3 = r0 (higher 32 bits of results are not written to register). 4. 2 if there is an instruction rewriting the psw contents immediately before. 5. in case of no wait states (3 + number of read access wait states). 6. n is the total number of cycles to load registers in list12 (depends on the number of wait states, n is the number of registers in list12 if no wait states. the operation when n = 0 is the same as when n = 1). 7. the nb85e and nb85et do not support instructions for the debug function. remarks 1. operand convention symbol meaning reg1 general register (used as source register) reg2 general register (mainly used as destination register. some are also used as source registers.) reg3 general register (mainly used as remainder of division results or higher 32 bits of multiply results) bit#3 3-bit data for bit number specification imm -bit immediate data disp -bit displacement data regid system register number vector 5-bit data for trap vector (00h to 1fh) specification cccc 4-bit data c ondition code specification sp stack pointer (r3) ep element pointer (r30) list list of registers ( is a maximum number of registers) 2. execution clock convention symbol meaning i when other instruction is executed immediately after executing an instruction (issue) r when the same instruction is repeatedly executed immediately after the instruction has been executed (repeat) l when a subsequent instruction uses the result of execution of the preceding instruction immediately after its execution (latency) chapter 5 instruction 162 user?s manual u14559ej2v0um table 5-7. list of number of instruction execution clock cycles (v850e/ma1, v850e/ma2, v850e/ia1, and v850e/ia2) (1/3) number of execution clocks type of instruction mnemonic operand byte irl ld.b disp16 [reg1] , reg2 4 1 1 note 1 ld.h disp16 [reg1] , reg2 4 1 1 note 1 ld.w disp16 [reg1] , reg2 4 1 1 note 1 ld.bu disp16 [reg1] , reg2 4 1 1 note 1 ld.hu disp16 [reg1] , reg2 4 1 1 note 1 sld.b disp7 [ep] , reg2 2 1 1 note 2 sld.bu disp4 [ep] , reg2 2 1 1 note 2 sld.h disp8 [ep] , reg2 2 1 1 note 2 sld.hu disp5 [ep] , reg2 2 1 1 note 2 load instructions sld.w disp8 [ep] , reg2 2 1 1 note 2 st.b reg2, disp16 [reg1] 4 1 1 1 st.h reg2, disp16 [reg1] 4 1 1 1 st.w reg2, disp16 [reg1] 4 1 1 1 sst.b reg2, disp7 [ep] 2 1 1 1 sst.h reg2, disp8 [ep] 2 1 1 1 store instructions sst.w reg2, disp8 [ep] 2 1 1 1 mul reg1, reg2, reg3 4 1 2 note 3 2 mul imm9, reg2, reg3 4 1 2 note 3 2 mulh reg1, reg2 2 1 1 2 mulh imm5, reg2 2 1 1 2 mulhi imm16, reg1, reg2 4 1 1 2 mulu reg1, reg2, reg3 4 1 2 note 3 2 multiply instructions mulu imm9, reg2, reg3 4 1 2 note 3 2 add reg1, reg2 2 1 1 1 add imm5, reg2 2 1 1 1 addi imm16, reg1, reg2 4 1 1 1 cmov cccc, r eg1, reg2, reg3 4 1 1 1 cmov cccc, imm5, r eg2, reg3 4 1 1 1 cmp reg1, reg2 2 1 1 1 cmp imm5, reg2 2 1 1 1 div reg1, reg2, reg3 4 35 35 35 divh reg1, reg2 2 35 35 35 divh reg1, reg2, reg3 4 35 35 35 divhu reg1, reg2, reg3 4 34 34 34 divu reg1, reg2, reg3 4 34 34 34 mov reg1, reg2 2 1 1 1 mov imm5, reg2 2 1 1 1 mov imm32, reg1 6 2 2 2 arithmetic operation instructions movea imm16, reg1, reg2 4 1 1 1 chapter 5 instruction 163 user?s manual u14559ej2v0um table 5-7. list of number of instruction execution clock cycles (v850e/ma1, v850e/ma2, v850e/ia1, and v850e/ia2) (2/3) number of execution clocks type of instruction mnemonic operand byte irl movhi imm16, reg1, reg2 4 1 1 1 sasf cccc, reg2 4 1 1 1 setf cccc, reg2 4 1 1 1 sub reg1, reg2 2 1 1 1 arithmetic operation instructions subr reg1, reg2 2 1 1 1 satadd reg1, reg2 2 1 1 1 satadd imm5, reg2 2 1 1 1 satsub reg1, reg2 2 1 1 1 satsubi imm16, reg1, reg2 4 1 1 1 saturated operation instructions satsubr reg1, reg2 2 1 1 1 and reg1, reg2 2 1 1 1 andi imm16, reg1, reg2 4 1 1 1 bsh reg2, reg3 4 1 1 1 bsw reg2, reg3 4 1 1 1 hsw reg2, reg3 4 1 1 1 not reg1, reg2 2 1 1 1 or reg1, reg2 2 1 1 1 ori imm16, reg1, reg2 4 1 1 1 sar reg1, reg2 4 1 1 1 sar imm5, reg2 2 1 1 1 shl reg1, reg2 4 1 1 1 shl imm5, reg2 2 1 1 1 shr reg1, reg2 4 1 1 1 shr imm5, reg2 2 1 1 1 sxb reg1 2 1 1 1 sxh reg1 2 1 1 1 tst reg1, reg2 2 1 1 1 xor reg1, reg2 2 1 1 1 xori imm16, reg1, reg2 4 1 1 1 zxb reg1 2 1 1 1 logical operation instructions zxh reg1 2 1 1 1 disp9 (when condition is satisfied) 2 3 note 4 3 note 4 3 note 4 bcond disp9 (when condition is not satisfied) 2 111 jarl disp22, reg2 4 3 3 3 jmp [reg1] 2 4 4 4 branch instructions jr disp22 4 3 3 3 chapter 5 instruction 164 user?s manual u14559ej2v0um table 5-7. list of number of instruction execution clock cycles (v850e/ma1, v850e/ma2, v850e/ia1, and v850e/ia2) (3/3) number of execution clocks type of instruction mnemonic operand byte irl clr1 bit#3, disp16 [reg1] 4 3 note 5 3 note 5 3 note 5 clr1 reg2, [reg1] 4 3 note 5 3 note 5 3 note 5 not1 bit#3, disp16 [reg1] 4 3 note 5 3 note 5 3 note 5 not1 reg2, [reg1] 4 3 note 5 3 note 5 3 note 5 set1 bit#3, disp16 [reg1] 4 3 note 5 3 note 5 3 note 5 set1 reg2, [reg1] 4 3 note 5 3 note 5 3 note 5 tst1 bit#3, disp16 [reg1] 4 3 note 5 3 note 5 3 note 5 bit manipulation instructions tst1 reg2, [reg1] 4 3 note 5 3 note 5 3 note 5 callt imm6 2 5 5 5 ctret ? 4 4 4 4 di ? 4 111 dispose imm5, list12 4 n+1 note 6 n+1 note 6 n+1 note 6 dispose imm5, list12, [reg1] 4 n+3 note 6 n+3 note 6 n+3 note 6 ei ? 4 111 halt ? 4 111 ldsr reg2, regid 4 1 1 1 nop ? 2 111 prepare list12, imm5 4 n+1 note 6 n+1 note 6 n+1 note 6 prepare list12, imm5, sp 4 n+2 note 6 n+2 note 6 n+2 note 6 prepare list12, imm5, imm16 6 n+2 note 6 n+2 note 6 n+2 note 6 prepare list12, imm5, imm32 8 n+3 note 6 n+3 note 6 n+3 note 6 reti ? 4 444 stsr regid, reg2 4 1 1 1 switch reg1 2 5 5 5 special instructions trap vector 4 4 4 4 dbret ? 4 4 4 4 debug function instructions dbtrap ? 2 444 undefined instruction code 4 3 3 3 notes 1. depends on the number of wait states (2 if no wait states). 2. depends on the number of wait states (1 if no wait states). 3. 1 clock shortened if reg2 = reg3 (lower 32 bits of results are not written to register) or reg3 = r0 (higher 32 bits of results are not written to register). 4. 2 if there is an instruction rewriting the psw contents immediately before. 5. in case of no wait states (3 + number of read access wait states). 6. n is the total number of cycles to load registers in list12 (depends on the number of wait states, n is the number of registers in list12 if no wait states. the operation when n = 0 is the same as when n = 1). chapter 5 instruction 165 user?s manual u14559ej2v0um remarks 1. operand convention symbol meaning reg1 general register (used as source register) reg2 general register (mainly used as destination register. some are also used as source registers.) reg3 general register (mainly used as remainder of division results or higher 32 bits of multiply results) bit#3 3-bit data for bit number specification imm -bit immediate data disp -bit displacement data regid system register number vector 5-bit data for trap vector (00h to 1fh) specification cccc 4-bit data c ondition code specification sp stack pointer (r3) ep element pointer (r30) list list of registers ( is a maximum number of registers) 2. execution clock convention symbol meaning i when other instruction is executed immediately after executing an instruction (issue) r when the same instruction is repeatedly executed immediately after the instruction has been executed (repeat) l when a subsequent instruction uses the result of execution of the preceding instruction immediately after its execution (latency) 166 user?s manual u14559ej2v0um chapter 6 interrupt and exception interrupts are events that occur independently of the program execution and are divided into two types: maskable interrupts and non-maskable interrupts (nmi). in contrast, exceptions are events whose occurrence is dependent on the program execution and are divided into three types: software exception, exception trap, and debug trap. when an interrupt or exception occurs, control is transferred to a handler whose address is determined by the source of the interrupt or exception. the source of the interrupt/exception is specified by the exception code that is stored in the exception cause register (ecr). each handler analyzes the ecr register and performs appropriate interrupt servicing or exception processing. the restore pc and restore psw are written to the status saving registers (eipc, eipsw or fepc, fepsw). to restore execution from interrupt or software exception processing, use the reti instruction. to restore execution from exception trap or debug trap, use the dbret instruction. read the restore pc and restore psw from the status saving register, and transfer control to the restore pc. table 6-1. interrupt/exception codes interrupt/exception source name trigger classification exception code handler address restore pc nmi0 input interrupt 0010h 00000010h next pc note 2 nmi1 input interrupt 0020h 00000020h next pc notes 2, 3 non-maskable interrupt (nmi) note 1 nmi2 input note 4 interrupt 0030h 00000030h next pc notes 2, 3 maskable interrupt note 5 interrupt note 5 note 6 next pc note 2 trap0n (n = 0 to fh) trap instruction exception 004nh 00000040h next pc software exception trap1n (n = 0 to fh) trap instruction exception 005nh 00000050h next pc exception trap (ilgop) illegal instruction code exception 0060h 00000060h next pc note 7 debug trap note 8 dbtrap instruction note 8 exception 0060h 00000060h next pc notes 1. nmi0 input is the only generation source for the v850e/ma1, v850e/ma2, v850e/ia1, or v850e/ia2. 2. except when an interrupt is acknowledged during execution of the one of the instructions listed below (if an interrupt is acknowledged during instruction execution, execution is stopped, and then resumed after the completion of interrupt servicing). ? load instructions (sld.b, sld.bu, sld.h, sld.hu, sld.w), divide instructions (div, divh, divu, divhu) ? prepare, dispose instruction (only if an interrupt is generated before the stack pointer is updated) 3. the pc cannot be restored by the reti instruction. perform a system reset after interrupt servicing. 4. acknowledged even if the np flag of psw is set to 1. 5. differs depending on the type of the interrupts. 6. higher 16 bits are 0000h and lower 16 bits are the same value as the exception code. 7. the execution address of the illegal instruction is obtained by ?restore pc ? 4?. 8. not supported in the nb85e and nb85et remark restore pc: pc value saved to the eipc or fepc when interrupt/exception processing is started next pc: pc value that starts processing after interrupt/exception processing chapter 6 interrupt and exception 167 user?s manual u14559ej2v0um 6.1 interrupt servicing 6.1.1 maskable interrupt the maskable interrupt can be masked by the interrupt control register of the interrupt controller (intc). the intc issues an interrupt request to the cpu, based on the acknowledged interrupt with the highest priority. if a maskable interrupt occurs due to interrupt request input (int input), the cpu performs the following steps, and transfers control to the handler routine. (1) saves restore pc to eipc. (2) saves current psw to eipsw. (3) writes exception code to lower half-word of ecr (eicc). (4) sets id flag of psw to 1 and clears ep flag to 0. (5) sets handler address for each interrupt to pc and transfers control. the eipc and eipsw are used as the status saving registers. int inputs are held pending in the interrupt controller (intc) when one of the following two conditions occur: when the int input is masked by its interrupt controller, or when an interrupt service routine is currently being executed (when the np flag of the psw is 1 or when the id flag of the psw is 1). interrupts are enabled by clearing the mask condition or by setting the np and id flags of the psw to 0 with the ldsr instruction, which will be enabling new maskable interrupt servicing by a pending int input. the eipc and eipsw registers must be saved by program to enable nesting of interrupts because there is only one set of eipc and eipsw is provided. maskable interrupt servicing format is shown below. chapter 6 interrupt and exception 168 user?s manual u14559ej2v0um figure 6-1. maskable interrupt servicing format interrupt request input (int input) xxif = 1 no interrupt request? xxmk = 0 no is the interrupt mask released? yes yes no no no maskable interrupt request interrupt request pending psw.np = 0 psw.id = 0 no no interrupt servicing pending yes yes interrupt servicing cpu processing intc processing yes yes yes priority higher than that of interrupt currently serviced? priority higher than that of other interrupt request? highest default priority of interrupt requests with the same priority? eipc eipsw ecr.eicc psw.ep psw.id pc restore pc psw exception code 0 1 handler address chapter 6 interrupt and exception 169 user ? s manual u14559ej2v0um 6.1.2 non-maskable interrupt the non-maskable interrupt cannot be disabled by an instruction and therefore can always be acknowledged. the non-maskable interrupt is generated by the nmi input. when the non-maskable interrupt is generated, the cpu performs the following steps, and transfers control to the handler routine. (1) saves restore pc to fepc. (2) saves current psw to fepsw. (3) writes exception code (0010h) to higher half-word of ecr (fecc). (4) sets np and id flags of psw to 1 and clears ep flag to 0. (5) sets handler address for the non-maskable interrupt to pc and transfers control. the fepc and fepsw are used as the status saving registers. non-maskable interrupts are held pending in the interrupt controller when another non-maskable interrupt is currently being executed (when the np flag of the psw is 1). non-maskable interrupts are enabled by setting the np flag of the psw to 0 with the reti and ldsr instructions, which will be enabling new non-maskable interrupt servicing by a pending non-maskable interrupt request. in the case of nb85e, nb85et, NU85E, or NU85Et, only when the nmi2 is generated during the interrupt servicing of nmi0 and nmi1, nmi2 servicing is executed regardless of the value of np flag. non-maskable interrupt servicing format is shown below. figure 6-2. non-maskable interrupt servicing format psw.np = 0 fepc fepsw ecr.fecc psw.np psw.ep psw.id pc restore pc psw exception code 1 0 1 handler address no yes nmi input interrupt servicing interrupt request pending intc acknowledgement cpu processing non-maskable interrupt request chapter 6 interrupt and exception 170 user ? s manual u14559ej2v0um 6.2 exception processing 6.2.1 software exception a software exception is generated when the trap instruction is executed and is always acknowledged. if a software exception occurs, the cpu performs the following steps, and transfers control to the handler routine. (1) saves restore pc to eipc. (2) saves current psw to eipsw. (3) writes exception code to lower 16 bits (eicc) of ecr (interrupt source). (4) sets ep and id flags of psw to 1. (5) sets handler address (00000040h or 00000050h) for software exception to pc and transfers control. software exception processing format is shown below. figure 6-3. software exception processing format eipc eipsw ecr.eicc psw.ep psw.id pc restore pc psw exception code 1 1 handler address trap instruction cpu processing exception processing chapter 6 interrupt and exception 171 user ? s manual u14559ej2v0um 6.2.2 exception trap an exception trap is an exception requested when an instruction is illegally executed. the illegal opcode trap (ilgop) is the exception trap. an illegal opcode instruction has an instruction code with an opcode (bits 10 through 5) of 111111b and a sub- opcode (bits 26 through 23) of 0111b through 1111b and a sub-opcode (bit 16) of 0b. when this kind of an illegal opcode instruction is executed, an exception trap occurs. figure 6-4. illegal instruction code 011 1 111 1 0 15 13 12 11 10 5 4 0 31 27 26 23 22 21 20 17 16 111111 to remark : don ? t care, : opcode/sub-opcode if an exception trap occurs, the cpu performs the following steps, and transfers control to the handler routine. (1) saves restore pc to dbpc. (2) saves current psw to dbpsw. (3) sets np, ep, and id flags of psw to 1. (4) sets handler address (00000060h) for exception trap to pc and transfers control. exception trap processing format is shown below. figure 6-5. exception trap processing format dbpc dbpsw psw.np psw.ep psw.id pc restore pc psw 1 1 1 00000060h exception trap (ilgop) occurs cpu processing exception processing caution the operation when executing the instruction not defined as an instruction or illegal instruction is not guaranteed. remark the execution address of the illegal instruction is obtained by ? restore pc ? 4 ? . chapter 6 interrupt and exception 172 user ? s manual u14559ej2v0um 6.2.3 debug trap a debug trap is generated when the dbtrap instruction is executed and is always acknowledged. if a debug trap occurs, the cpu performs the following steps. (1) saves restore pc to dbpc. (2) saves current psw to dbpsw. (3) sets np, ep, and id flags of psw to 1. (4) sets dm flag of dir to 1 when a debug trap occurs. (5) sets handler address (00000060h) for debug trap to pc and transfers control. caution the nb85e and nb85et do not support debug trap. debug trap processing format is shown below. figure 6-6. debug trap processing format dbpc dbpsw psw.np psw.ep psw.id dir.dm pc restore pc psw 1 1 1 1 00000060h dbtrap instruction cpu processing debug monitor routine processing chapter 6 interrupt and exception 173 user?s manual u14559ej2v0um 6.3 restoring from interrupt/exception processing 6.3.1 restoring from interrupt and software exception all restoration from interrupt servicing and software exception is executed by the reti instruction. with the reti instruction, the cpu performs the following steps, and transfers control to the address of the restore pc. (1) if the ep flag of the psw is 0 and the np flag of the psw is 1, the restore pc and psw are read from the fepc and fepsw. otherwise, the restore pc and psw are read from the eipc and eipsw. (2) control is transferred to the address of the restored pc and psw. when execution has returned from each interrupt servicing, the np and ep flags of the psw must be set to the following values by using the ldsr instruction immediately before the reti instruction, in order to restore the pc and psw normally: ? to restore from non-maskable interrupt servicing note : np flag of psw = 1, ep flag = 0 ? to restore from maskable interrupt servicing: np flag of psw = 0, ep flag = 0 ? to restore from exception processing: ep flag of psw = 1 note in the case of nb85e, nb85et, NU85E, or NU85Et, nmi1 and nmi2 cannot be restored by the reti instruction. execute the system reset after the interrupt servicing. nmi2 can be acknowledged even if the np flag of psw is set to 1. restoration from interrupt/exception processing format is shown below. figure 6-7. restoration from interrupt/software exception processing format psw.ep = 0 psw.np = 0 pc psw eipc eipsw no pc psw fepc fepsw no yes yes chapter 6 interrupt and exception 174 user ? s manual u14559ej2v0um 6.3.2 restoring from exception trap and debug trap restoration from exception trap and debug trap is executed by the dbret instruction. with the dbret instruction, the cpu performs the following steps, and transfers control to the address of the restore pc. (1) the restore pc and psw are read from the dbpc and dbpsw. (2) control is transferred to the address of the restored pc and psw. (3) if restored from exception trap or debug trap, dm flag of dir is cleared to 0. restoration from exception trap/debug trap processing format is shown below. figure 6-8. restoration from exception trap/debug trap processing format pc psw dir.dm dbpc dbpsw 0 dbret instruction jump to address of restore pc 175 user?s manual u14559ej2v0um chapter 7 reset 7.1 register status after reset when a low-level signal is input to the reset pin, the system is reset, and program registers and system registers are set in the status shown in table 7-1. when the reset signal goes high, the reset status is cleared, and program execution begins. if necessary, initialize the contents of each register by program control. table 7-1. register status after reset register status after reset (initial value) general register (r0) 00000000h (fixed) general register (r1 to r31) undefined program registers program counter (pc) 00000000h interrupt status saving register (eipc) 0xxxxxxxh interrupt status saving register (eipsw) 00000 xxxh nmi status saving register (fepc) 0xxxxxxxh nmi status saving register (fepsw) 00000 xxxh exception cause register (ecr) 00000000h program status word (psw) 00000020h callt caller status saving register (ctpc) 0xxxxxxxh callt caller status saving register (ctpsw) 00000 xxxh exception/debug trap status saving register (dbpc) 0 xxxxxxxh exception/debug trap status saving register (dbpsw) 00000 xxxh callt base pointer (ctbp) 0xxxxxxxh debug interface register (dir) 00000040h breakpoint control register 0 (bpc0) 00xxxxx0h breakpoint control register 1 (bpc1) 00xxxxx0h program id register (asid) 000000xxh breakpoint address setting register 0 (bpav0) 0 xxxxxxxh breakpoint address setting register 1 (bpav1) 0 xxxxxxxh breakpoint address mask register 0 (bpam0) 0 xxxxxxxh breakpoint address mask register 1 (bpam1) 0 xxxxxxxh breakpoint data setting register 0 (bpdv0) undefined breakpoint data setting register 1 (bpdv1) undefined breakpoint data mask register 0 (bpdm0) undefined system registers breakpoint data mask register 1 (bpdm1) undefined remark x: undefined chapter 7 r eset 176 user?s manual u14559ej2v0um 7.2 starting up the cpu begins program execution from address 00000000h after it has been reset. after reset, no immediate interrupt requests are acknowledged. to enable interrupts by program, clear the id flag of the psw to 0. 177 user?s manual u14559ej2v0um chapter 8 pipeline the v850e1 cpu is based on the risc architecture and executes almost all the instructions in one clock cycle under control of a 5-stage pipeline. the instruction execution sequence usually consists of five stages including fetch (if) to write back (wb) stages. the execution time of each stage differs depending on the type of the instruction and the type of the memory to be accessed. as an example of pipeline operation, figure 8-1 shows the processing of the cpu when 9 standard instructions are executed in succession. figure 8-1. example of executing nine standard instructions if id ex mem wb <1> <2> <3> <4> <5> if id ex mem wb if id ex mem wb if id ex mem wb if id ex mem wb if id ex mem wb <6> <7> <8> <9> <10> if id ex mem wb if id ex mem wb if id ex mem wb <11> <12> <13> instruction 1 ...................................... ............................ ...... ................. ................................................. ............................................................ ...................................................................... ................................................................................. ........................................................................................... processing cpu performs simultaneously internal system clock time flow (state) executes instruction every 1 clock cycle instruction 2 instruction 3 instruction 4 instruction 5 instruction 6 instruction 7 instruction 8 instruction 9 end of instruc- tion 1 end of instruc- tion 9 end of instruc- tion 8 end of instruc- tion 7 end of instruc- tion 6 end of instruc- tion 5 end of instruc- tion 4 end of instruc- tion 3 end of instruc- tion 2 if (instruction fetch): instruction is fetched and fetch pointer is incremented. id (instruction decode): instruction is decoded, immediate data is generated, and register is read. ex (execution of alu, multiplier, and barrel shifter): the decoded instruction is executed. mem (memory access): the memory at specified address is accessed. wb (write back): the result of execution is written to register. <1> through <13> in the figure above indicate the states of the cpu. in each state, write back (wb) of instruction n, memory access (mem) of instruction n+1, execution (ex) of instruction n+2, decoding (id) of instruction n+3, and fetching (if) of instruction n+4 are simultaneously performed. it takes five clock cycles to process a standard instruction, including if stage to wb stage. because five instructions can be processed at the same time, however, a standard instruction can be executed in 1 clock on the average. chapter 8 pipeline 178 user?s manual u14559ej2v0um 8.1 features the v850e1 cpu, by optimizing the pipeline, improves the cpi (cycle per instruction) rate over the previous v850 cpu. the pipeline configuration of the v850e1 cpu is shown in figure 8-2. figure 8-2. pipeline configuration id ex df wb wb mem bcond/sld pipeline id if address calculation stage asynchronous wb pipeline master pipeline (v850 cpu compatible) load, store buffer (1 stage each) remark df (data fetch): execution data is transferred to the wb stage. chapter 8 pipeline 179 user?s manual u14559ej2v0um 8.1.1 non-blocking load/store as the pipeline does not stop during external memory access, efficient processing is possible. for example, figure 8-3 shows a comparison of pipeline operations between the v850 cpu and the v850e1 cpu when an add instruction is executed after the execution of a load instruction for external memory. figure 8-3. non-blocking load/store (a) previous version (v850 cpu): pipeline is stopped until mem stage is complete if id ex t1 mem (external memory) note t2 t3 wb if id ex (mem) wb if id mem wb ex load instruction add instruction next instruction note the basic bus cycle for the external memory is 3 clocks. (b) v850e1 cpu: efficient pipeline processing through use of asynchronous wb pipeline if id ex t1 mem (external memory) n o t e t2 wb if id ex wb df if id ex wb mem load instruction add instruction next instruction note the basic bus cycle for the external memory of memc is 2 clocks. (1) v850 cpu the ex stage of the add instruction is usually executed in 1 clock. however, a wait time is generated in the ex stage of the add instruction during execution of the mem stage of the previous load instruction. this is because the same stage of the 5 instructions on the pipeline cannot be executed in the same internal clock interval. this also causes a wait time to be generated in the id stage of the next instruction after the add instruction. (2) v850e1 cpu an asynchronous wb pipeline for the instructions that are necessary for the mem stage is provided in addition to the master pipeline. the mem stage of the load instruction is therefore processed on this asynchronous wb pipeline. because the add instruction is processed on the master pipeline, a wait time is not generated, making it possible to execute instructions efficiently as shown in figure 8-3. chapter 8 pipeline 180 user?s manual u14559ej2v0um 8.1.2 2-clock branch when executing a branch instruction, the branch destination is decided in the id stage. in the case of the conventional v850 cpu, the branch destination of when the branch instruction is executed was decided after execution of the ex stage, but in the case of the v850e1 cpu, due to the addition of a address calculation stage for branch/sld instruction, the branch destination is decided in the id stage. therefore, it is possible to fetch the branch destination instruction 1 clock faster than in the conventional v850 cpu. figure 8-4 shows a comparison between the v850 cpu and the v850e1 cpu of pipeline operations with branch instructions. figure 8-4. pipeline operations with branch instructions (a) previous version (v850 cpu) if id ex wb branch instruction branch destination instruction if id ex wb mem mem branch destination decided in ex stage 3 clocks (b) v850e1 cpu if id wb if id ex wb mem mem branch destination decided in id stage ex branch instruction branch destination instruction 2 clocks remark the v850e/ma1, v850e/ia1, and v850e/ia2 executes interleave access to the internal flash memory or internal mask rom. therefore, it takes two clocks to an instruction fetch immediately after an interrupt has occurred or after a branch destination instruction has been executed. consequently, it takes three clocks to execute the id stage of the branch destination instruction. example if if id ex mem wb if if id ex mem wb if if id if if id ex mem wb if if id ex mem wb instruction 1 instruction 2 instruction 3 branch instruction branch destination instruction interleave access 3 clocks chapter 8 pipeline 181 user ? s manual u14559ej2v0um 8.1.3 efficient pipeline processing because the v850e1 cpu has an id stage for branch/sld instructions in addition to the id stage on the master pipeline, it is possible to perform efficient pipeline processing. figure 8-5 shows an example of a pipeline operation where the next branch instruction was fetched in the if stage of the add instruction (instruction fetch from the rom directly connected to the dedicated bus is performed in 32-bit units. both add instructions and branch instructions in figure 8-5 use a 16-bit format instruction). figure 8-5. parallel execution of branch instructions (a) previous version (v850 cpu) if id id ex if ex (mem) wb mem wb if id ex mem add instruction branch instruction branch destination instruction 5 clocks (b) v850e1 cpu if id ex df wb mem wb if id ex mem id wb ex add instruction branch instruction branch destination instruction 3 clocks if (1) v850 cpu although the instruction codes up to the next branch instruction are fetched in the if stage of the add instruction, the id stage of the add instruction and the id stage of the branch instruction cannot execute together within the same clock. therefore, it takes 5 clocks from the branch instruction fetch to the branch destination instruction fetch. (2) v850e1 cpu because v850e1 cpu has an id stage for branch/sld instructions in addition to the id stage on the master pipeline, the parallel execution of the id stage of the add instruction and the id stage of the branch instruction within the same clock is possible. therefore, it takes only 3 clocks from the branch instruction fetch start to the branch destination instruction completion. caution be aware that the sld and bcond instructions are sometimes executed at the same time as other 16-bit format instructions. for example, if the sld and nop instructions are executed simultaneously, the nop instruction may keep the delay time from being generated. chapter 8 pipeline 182 user ? s manual u14559ej2v0um 8.2 pipeline flow during execution of instructions this section explains the pipeline flow during the execution of instructions. in pipeline processing, the cpu is already processing the next instruction when the memory or i/o write cycle is generated. as a result, i/o manipulations and interrupt request masking will be reflected later than next instructions are issued (id stage). (1) nb85e, nb85et, NU85E, NU85Et when a dedicated interrupt controller (intc) is connected to the npb (nec peripheral bus), maskable interrupt acknowledgement is disabled from the next instruction because the cpu detects access to the intc and performs interrupt request mask processing. (2) v850e/ma1, v850e/ma2, v850e/ia1, v850e/ia2 when an interrupt mask manipulation is performed, maskable interrupt acknowledged is disabled from the instruction immediately after an instruction because the cpu detects access to the internal intc (id stage) and performs interrupt request mask processing. 8.2.1 load instructions caution due to non-blocking control, there is no guarantee that the bus cycle is complete between the mem stages. however, when accessing the peripheral i/o area, blocking control is effected, making it possible to wait for the end of the bus cycle at the mem stage. for the nb85e, nb85et, NU85E, or NU85Et, non-blocking control is used for access to the programmable peripheral i/o area. (1) ld instructions [instructions] ld.b, ld.bu, ld.h, ld.hu, ld.w [pipeline] <1> <2> <3> <4> <5> <6> ld instruction if id ex mem wb next instruction if id ex mem wb [description] the pipeline consists of 5 stages, if, id, ex, mem, and wb. if an instruction using the execution result is placed immediately after the ld instruction, data wait time occurs. (2) sld instructions [instructions] sld.b, sld.bu, sld.h, sld.hu, sld.w [pipeline] <1> <2> <3> <4> <5> <6> sld instruction if id mem wb next instruction if id ex mem wb [description] the pipeline consists of 4 stages, if, id, mem, and wb. if an instruction using the execution result is placed immediately after the sld instruction, data wait time occurs. chapter 8 pipeline 183 user ? s manual u14559ej2v0um 8.2.2 store instructions caution due to non-blocking control, there is no guarantee that the bus cycle is complete between the mem stages. however, when accessing the peripheral i/o area, blocking control is effected, making it possible to wait for the end of the bus cycle at the mem stage. for the nb85e, nb85et, NU85E, or NU85Et, non-blocking control is used for access to the programmable peripheral i/o area. [instructions] st.b, st.h, st.w, sst.b, sst.h, sst.w <1> <2> <3> <4> <5> <6> [pipeline] store instruction if id ex mem wb next instruction if id ex mem wb [description] the pipeline consists of 5 stages, if, id, ex, mem, and wb. however, no operation is performed in the wb stage, because no data is written to registers. 8.2.3 multiply instructions [instructions] mul, mulh, mulhi, mulu [pipeline] (a) when next instruction is not multiply instruction <1> <2> <3> <4> <5> <6> multiply instruction if id ex1 ex2 wb next instruction if id ex mem wb (b) when next instruction is multiply instruction <1> <2> <3> <4> <5> <6> multiply instruction 1 if id ex1 ex2 wb multiply instruction 2 if id ex1 ex2 wb [description] the pipeline consists of 5 stages, if, id, ex1, ex2, and wb. the ex stage takes 2 clocks because it is executed by a multiplier. ex1 and ex2 stages (different from the normal ex stage) can operate independently. therefore, the number of clocks for instruction execution is always 1 clock, even if several multiply instructions are executed in a row. however, if an instruction using the execution result is placed immediately after a multiply instruction, data wait time occurs. chapter 8 pipeline 184 user ? s manual u14559ej2v0um 8.2.4 arithmetic operation instructions (1) instructions other than divide/move word instructions [instructions] add, addi, cmov, cmp, mov, movea, movhi, sasf, setf, sub, subr <1> <2> <3> <4> <5> <6> [pipeline] arithmetic operation instruction if id ex df wb next instruction if id ex mem wb [description] the pipeline consists of 5 stages, if, id, ex, df, and wb. (2) move word instruction [instructions] mov imm32 <1> <2> <3> <4> <5> <6> <7> [pipeline] arithmetic operation instruction if id ex1 ex2 df wb next instruction if ? id ex mem wb ? : idle inserted for wait [description] the pipeline consists of 6 stages, if, id, ex1, ex2 (normal ex stage), df, and wb. (3) divide instructions [instructions] div, divh, divhu, divu [pipeline] (a) div, divh instructions <1> <2> <3> <4> <35> <36> <37> <38> <39> <40> <41> divide instruction if id ex1 ex2 ex33 ex34 ex35 df wb next instruction if ?? ?? id ex mem wb next to next instruction if id ex mem wb ? : idle inserted for wait (b) divhu, divu instructions <1> <2> <3> <4> <35> <36> <37> <38> <39> <40> divide instruction if id ex1 ex2 ex33 ex34 df wb next instruction if ?? ? id ex mem wb next to next instruction if id ex mem wb ? : idle inserted for wait [description] the pipeline consists of 39 stages, if, id, ex1 to ex35 (normal ex stage), df, and wb for div and divh instructions. the pipeline consists of 38 stages, if, id, ex1 to ex34 (normal ex stage), df, and wb for divhu and divu instructions. [remark] if an interrupt occurs while a division instruction is executed, execution of the instruction is stopped, and the interrupt is processed, assuming that the return address is the first address of that instruction. after interrupt processing has been completed, the division instruction is executed again. in this case, general-purpose registers reg1 and reg2 hold the value before the instruction is executed. chapter 8 pipeline 185 user?s manual u14559ej2v0um 8.2.5 saturated operation instructions [instructions] satadd, satsub, satsubi, satsubr <1> <2> <3> <4> <5> <6> [pipeline] saturated operation instruction if id ex df wb next instruction if id ex mem wb [description] the pipeline consists of 5 stages, if, id, ex, df, and wb. 8.2.6 logical operation instructions [instructions] and, andi, bsh, bsw, hsw, not, or, ori, sar, shl, shr, sxb, sxh, tst, xor, xori, zxb, zxh <1> <2> <3> <4> <5> <6> [pipeline] logical operation instruction if id ex df wb next instruction if id ex mem wb [description] the pipeline consists of 5 stages, if, id, ex, df, and wb. 8.2.7 branch instructions (1) conditional branch instructions (except br instruction) [instructions] bcond instructions (bc, be, bge, bgt, bh, bl, ble, blt, bn, bnc, bne, bnh, bnl, bnv, bnz, bp, bsa, bv, bz) [pipeline] (a) when the condition is not satisfied <1> <2> <3> <4> <5> <6> conditional branch instruction if id ex mem wb next instruction if id ex mem wb (b) when the condition is satisfied <1> <2> <3> <4> <5> <6> <7> conditional branch instruction if id ex mem wb next instruction (if) branch destination instruction if id ex mem wb (if): instruction fetch that is not executed chapter 8 pipeline 186 user?s manual u14559ej2v0um [description] the pipeline consists of 5 stages, if, id, ex, mem, and wb. however, no operation is performed in the ex, mem, and wb stages, because the branch destination is decided in the id stage. (a) when the condition is not satisfied the number of execution clocks for the branch instruction is 1. (b) when the condition is satisfied the number of execution clocks for the branch instruction is 2. if stage of the next instruction of the branch instruction is not executed. if an instruction overwriting the contents of psw occurs immediately before, the number of execution clocks is 3 because of flag hazard occurrence. (2) br instruction, unconditional branch instructions (except jmp instruction) [instructions] br, jarl, jr [pipeline] <1> <2> <3> <4> <5> <6> <7> br instruction, unconditional branch instruction if id ex mem wb* next instruction (if) branch destination instruction if id ex mem wb (if): instruction fetch that is not executed wb*: no operation is performed in the case of the jr and br instructions but in the case of the jarl instruction, data is written to the restore pc. [description] the pipeline consists of 5 stages, if, id, ex, mem, and wb. however, no operation is performed in the ex, mem, and wb stages, because the branch destination is decided in the id stage. however, in the case of the jarl instruction, data is written to the restore pc in the wb stage. also, the if stage of the next instruction of the branch instruction is not executed. (3) jmp instruction [pipeline] <1> <2> <3> <4> <5> <6> <7> jmp instruction if id ex mem wb next instruction (if) branch destination instruction if id ex mem wb (if): instruction fetch that is not executed [description] the pipeline consists of 5 stages, if, id, ex, mem, and wb. however, no operation is performed in the ex, mem, and wb stages, because the branch destination is decided in the id stage. chapter 8 pipeline 187 user?s manual u14559ej2v0um 8.2.8 bit manipulation instructions (1) clr1, not1, set1 instructions [pipeline] <1> <2> <3> <4> <5> <6> <7> <8> <9> bit manipulation instruction if id ex1 mem ex2 mem wb next instruction if ?? id ex mem wb next to next instruction if id ex mem wb ?: idle inserted for wait [description] the pipeline consists of 7 stages, if, id, ex1, mem, ex2 (normal stage), mem, and wb. however, no operation is performed in the wb stage, because no data is written to registers. in the case of these instructions, the memory access is read modify write, the ex stage requires a total of 2 clocks, and the mem stage requires a total of 2 cycles. (2) tst1 instruction [pipeline] <1> <2> <3> <4> <5> <6> <7> <8> <9> bit manipulation instruction if id ex1 mem ex2 mem wb next instruction if ?? id ex mem wb next to next instruction if id ex mem wb ?: idle inserted for wait [description] the pipeline consists of 7 stages, if, id, ex1, mem, ex2 (normal stage), mem, and wb. however, no operation is performed in the second mem and wb stages, because there is no second memory access nor data write to registers. in all, this instruction requires 2 clocks. 8.2.9 special instructions (1) callt instruction [pipeline] <1> <2> <3> <4> <5> <6> <7> <8> <9> callt instruction if id mem ex mem wb next instruction (if) branch destination instruction if id ex mem wb (if): instruction fetch that is not executed [description] the pipeline consists of 6 stages, if, id, mem, ex, mem, and wb. however, no operation is performed in the second mem and wb stages, because there is no memory access and no data is written to registers. chapter 8 pipeline 188 user?s manual u14559ej2v0um (2) ctret instruction [pipeline] <1> <2> <3> <4> <5> <6> <7> ctret instruction if id ex mem wb next instruction (if) branch destination instruction if id ex mem wb (if): instruction fetch that is not executed [description] the pipeline consists of 5 stages, if, id, ex, mem, and wb. however, no operation is performed in the ex, mem, and wb stages, because the branch destination is decided in the id stage. (3) di, ei instructions <1> <2> <3> <4> <5> <6> [pipeline] di, ei instruction if id ex mem wb next instruction if id ex mem wb [description] the pipeline consists of 5 stages, if, id, ex, mem, and wb. however, no operation is performed in the mem and wb stages, because memory is not accessed and data is not written to registers. [remark] both the di and ei instructions do not sample an interrupt request. an interrupt is sampled as follows while these instructions are executed. instruction immediately before if id ex mem wb di, ei instruction if id ex mem wb instruction immediately after if id ex mem wb last sampling of interrupt before execution of ei or di instruction first sampling of interrupt after execution of ei or di instruction chapter 8 pipeline 189 user?s manual u14559ej2v0um (4) dispose instruction [pipeline] (a) when branch is not executed <1> <2> <3> <4> chapter 8 pipeline 190 user?s manual u14559ej2v0um (7) nop instruction <1> <2> <3> <4> <5> <6> [pipeline] nop instruction if id ex mem wb next instruction if id ex mem wb [description] the pipeline consists of 5 stages, if, id, ex, mem, and wb. however, no operation is performed in the ex, mem, and wb stages, because no operation and no memory access is executed, and no data is written to registers. caution be aware that the sld and bcond instructions are sometimes executed at the same time as other 16-bit format instructions. for example, if the sld and nop instructions are executed simultaneously, the nop instruction may keep the delay time from being generated. (8) prepare instruction [pipeline] <1> <2> <3> <4> chapter 8 pipeline 191 user?s manual u14559ej2v0um (10) switch instruction [pipeline] <1> <2> <3> <4> <5> <6> <7> <8> <9> <10> switch instruction if id ex1 mem ex2 mem wb next instruction (if) branch destination instruction if id ex mem wb (if): instruction fetch that is not executed [description] the pipeline consists of 7 stages, if, id, ex1 (normal ex stage), mem, ex2, mem, and wb. however, no operation is performed in the second mem and wb stages, because there is no memory access and no data is written to registers. (11) trap instruction <1> <2> <3> <4> <5> <6> <7> <8> [pipeline] trap instruction if id1 id2 ex df wb next instruction (if) next to next instruction (if) jump destination instruction if id ex mem wb (if): instruction fetch that is not executed id1: exception code (004nh, 005nh) detection (n = 0 to fh) id2: address generation [description] the pipeline consists of 6 stages, if, id1, id2, ex, df, and wb. the id stage requires 2 clocks. also, the if stages of the next instruction and next to next instruction are not executed. chapter 8 pipeline 192 user?s manual u14559ej2v0um 8.2.10 debug function instructions (1) dbret instruction <1> <2> <3> <4> <5> <6> <7> <8> [pipeline] dbret instruction if id1 id2 ex mem wb next instruction (if) next to next instruction (if) jump destination instruction if id ex mem wb (if): instruction fetch that is not executed id1: register selection id2: read dbpc [description] the pipeline consists of 6 stages, if, id1, id2, ex, mem, and wb. however, no operation is performed in the mem and wb stages, because the memory is not accessed and no data is written to registers. the id stage requires 2 clocks. also, the if stages of the next instruction and next to next instruction are not executed. (2) dbtrap instruction <1> <2> <3> <4> <5> <6> <7> <8> [pipeline] dbtrap instruction if id1 id2 ex df wb next instruction (if) next to next instruction (if) jump destination instruction if id ex mem wb (if): instruction fetch that is not executed id1: exception code (0060h) detection id2: address generation [description] the pipeline consists of 6 stages, if, id1, id2, ex, mem, and wb. the id stage requires 2 clocks. also, the if stages of the next instruction and next to next instruction are not executed. chapter 8 pipeline 193 user?s manual u14559ej2v0um 8.3 pipeline disorder the pipeline consists of 5 stages from if (instruction fetch) to wb (write back). each stage basically requires 1 clock for processing, but the pipeline may become disordered, causing the number of execution clocks to increase. this section describes the main causes of pipeline disorder. 8.3.1 alignment hazard if the branch destination instruction address is not word aligned (a1=1, a0=0) and is 4 bytes in length, it is necessary to repeat if twice in order to align instructions in word units. this is called an align hazard. for example, the instructions a to e are placed from address x0h, and that instruction b consists of 4 bytes, and the other instructions each consist of 2 bytes. in this case, instruction b is placed at x2h (a1=a0=0), and is not word aligned (a1=0, a0=0). therefore, when this instruction b becomes the branch destination instruction, an align hazard occurs. when an align hazard occurs, the number of execution clocks of the branch instruction becomes 4. figure 8-6. align hazard example (a) memory map (b) pipeline if id ex mem wb if branch instruction next instruction <1> <2> <3> <4> <5> <6> <7> <8> if1 if2 id ex mem wb if id ex mem wb <9> branch destination instruction (instruction b) branch destination's next instruction (instruction c) instruc- tion d instruc- tion e instruc- tion b instruc- tion c instruc- tion a instruc- tion b x8h x4h x0h 32 bits address of branch destination instruction (instruction b) if : instruction fetch that is not executed if1: first instruction fetch that occurs during align hazard. it is a 2-byte fetch that fetches the 2 bytes on the lower address of instruction b. if2: second instruction fetch that occurs during align hazard. it is normally a 4-byte fetch that fetches the 2 bytes on the upper address of instruction b in addition to instruction c (2-byte length). align hazards can be prevented through the following handling in order to obtain faster instruction execution. ? use 2-byte branch destination instruction. ? use 4-byte instructions placed at word boundaries (a1=0, a0=0) for branch destination instructions. chapter 8 pipeline 194 user?s manual u14559ej2v0um 8.3.2 referencing execution result of load instruction for load instructions (ld, sld), data read in the mem stage is saved during the wb stage. therefore, if the contents of the same register are used by the instruction immediately after the load instruction, it is necessary to delay the use of the register by this later instruction until the load instruction has ended using that register. this is called a hazard. the v850e1 cpu has an interlock function to automatically handle this hazard by delaying the id stage of the next instruction. the v850e1 cpu also has a short path that allows the data read during the mem stage to be used in the id stage of the next instruction. this short path allows data to be read with the load instruction during the mem stage and the use of this data in the id stage of the next instruction with the same timing. as a result of the above, when using the execution result in the instruction following immediately after, the number of execution clocks of the load instruction is 2. figure 8-7. example of execution result of load instruction if id ex mem wb if il id ex mem load instruction 1 (ld [r4], r6) instruction 2 (add 2, r6) wb if - id ex mem if id ex mem wb wb instruction 3 instruction 4 <1> <2> <3> <4> <5> <6> <7> <8> <9> il: idle inserted for data wait by interlock function -: idle inserted for wait : short path as shown in figure 8-7, when an instruction placed immediately after a load instruction uses its execution result, a data wait time occurs due to the interlock function, and the execution speed is lowered. this drop in execution speed can be avoided by placing instructions that use the execution result of a load instruction at least 2 instructions after the load instruction. chapter 8 pipeline 195 user?s manual u14559ej2v0um 8.3.3 referencing execution result of multiply instruction for multiply instructions (mulh, mulhi), the operation result is saved to the register in the wb stage. therefore, if the contents of the same register are used by the instruction immediately after the multiply instruction, it is necessary to delay the use of the register by this later instruction until the multiply instruction has ended using that register (occurrence of hazard). the v850e1 cpu?s interlock function delays the id stage of the instruction following immediately after. a short path is also provided that allows the ex2 stage of the multiply instruction and the multiply instruction?s operation result to be used in the id stage of the instruction following immediately after with the same timing. figure 8-8. example of execution result of multiply instruction if id ex1 ex2 wb if il id ex mem instruction 2 (add 2, r6) wb if - id ex mem if id ex mem wb wb instruction 3 instruction 4 <1> <2> <3> <4> <5> <6> multiply instruction 1 (mulh 3, r6) <7> <8> <9> il: idle inserted for data wait by interlock function -: idle inserted for wait : short path as shown in figure 8-8, when an instruction placed immediately after a multiply instruction uses its execution result, a data wait time occurs due to the interlock function, and the execution speed is lowered. this drop in execution speed can be avoided by placing instructions that use the execution result of a multiply instruction at least 2 instructions after the multiply instruction. chapter 8 pipeline 196 user ? s manual u14559ej2v0um 8.3.4 referencing execution result of ldsr instruction for eipc and fepc when using the ldsr instruction to set the data of the eipc and fepc system registers, and immediately after referencing the same system registers with the stsr instruction, the use of the system registers for the stsr instruction is delayed until the setting of the system registers with the ldsr instruction is completed (occurrence of hazard). the v850e1 cpu ? s interlock function delays the id stage of the stsr instruction immediately after. as a result of the above, when using the execution result of the ldsr instruction for eipc and fepc for an stsr instruction following immediately after, the number of execution clocks of the ldsr instruction becomes 3. figure 8-9. example of referencing execution result of ldsr instruction for eipc and fepc if id ex mem if il il ex ldsr instruction (ldsr r6, 0) note stsr instruction (stsr 0, r7) note mem if - id ex mem if id ex mem wb wb next instruction next to next instruction wb wb id - <1> <2> <3> <4> <5> <6> <7> <8> <9> <10> il: idle inserted for data wait by interlock function -: idle inserted for wait note system register 0 used for the ldsr and stsr instructions designates eipc. as shown in figure 8-9, when an stsr instruction is placed immediately after an ldsr instruction that uses the operand eipc or fepc, and that stsr instruction uses the ldsr instruction execution result, the interlock function causes a data wait time to occur, and the execution speed is lowered. this drop in execution speed can be avoided by placing stsr instructions that reference the execution result of the preceding ldsr instruction at least 3 instructions after the ldsr instruction. 8.3.5 cautions when creating programs when creating programs, pipeline disorder can be avoided and instruction execution speed can be raised by observing the following cautions. ? place instructions that use the execution result of load instructions (ld, sld) at least 2 instructions after the load instruction. ? place instructions that use the execution result of multiply instructions (mulh, mulhi) at least 2 instructions after the multiply instruction. ? if using the stsr instruction to read the setting results written to the eipc or fepc registers with the ldsr instruction, place the stsr instruction at least 3 instructions after the ldsr instruction. ? for the first branch destination instruction, use a 2-byte instruction, or a 4-byte instruction placed at the word boundary. chapter 8 pipeline 197 user ? s manual u14559ej2v0um 8.4 additional items related to pipeline 8.4.1 harvard architecture the v850e1 cpu uses the harvard architecture to operate an instruction fetch path from internal rom and a memory access path to internal ram independently. this eliminates path arbitration conflicts between the if and mem stages and allows orderly pipeline operation. (1) v850e1 cpu (harvard architecture) the mem stage of instruction 1 and the if stage of instruction 4, as well as the mem stage of instruction 2 and the if stage of instruction 5 can be executed simultaneously with orderly pipeline operation. if id ex mem if id ex wb instruction 1 instruction 2 if ex mem wb ex mem wb instruction 3 instruction 4 wb mem id instruction 5 id ex mem wb if if id <1> <2> <3> <4> <5> <6> <7> <8> <9> (2) not v850e1 cpu (other than harvard architecture) the mem stage of instruction 1 and the if stage of instruction 4, in addition to the mem stage of instruction 2 and the if stage of instruction 5 are in contention, causing path waiting to occur and slower execution time due to disorderly pipeline operation. if id ex mem if id - mem instruction 1 instruction 2 if id - ex - id ex instruction 3 instruction 4 wb ex - instruction 5 if if id ex <1> <2> <3> <4> <5> <6> <7> <8> <9> <10> wb mem mem mem <11> wb wb wb -: idle inserted for wait chapter 8 pipeline 198 user ? s manual u14559ej2v0um 8.4.2 short path the v850e1 cpu provides on chip a short path that allows the use of the execution result of the preceding instruction by the following instruction before write back (wb) is completed for the previous instruction. example 1. execution result of arithmetic operation instruction and logical operation used by instruction following immediately after ? v850e1 cpu (on-chip short path) the execution result of the preceding instruction can be used for the id stage of the instruction following immediately after as soon as the result is out (ex stage), without having to wait for write back to be completed. if id ex mem wb if id ex mem wb add 2, r6 mov r6, r7 <1> <2> <3> <4> <5> <6> ? not v850e1 cpu (no short path) the id stage of the instruction following immediately after is delayed until write back of the previous instruction is completed. if id ex wb if--idex add 2, r6 mov r6, r7 mem wb <1> <2> <3> <4> <5> <6> <7> <8> mem -: idle inserted for wait : short path chapter 8 pipeline 199 user ? s manual u14559ej2v0um example 2. data read from memory by the load instruction used by instruction following immediately after ? v850e1 cpu (on-chip short path) the execution result of the preceding instruction can be used for the id stage of the instruction following immediately after as soon as the result is out (mem stage), without having to wait for write back to be completed. if id ex mem wb if il id ex mem ld [r4], r6 add 2, r6 wb id ex mem id ex mem wb wb next instruction next to next instruction <1> <2> <3> <4> <5> <6> <7> <8> <9> if - if ? not v850e1 cpu (no short path) the id stage of the instruction following immediately after is delayed until write back of the previous instruction is completed. if id ex mem wb if--idex ld [r4], r6 add 2, r6 mem if id ex if id ex mem mem next instruction next to next instruction wb wb wb <1> <2> <3> <4> <5> <6> <7> <8> <9> <10> il: idle inserted for data wait by interlock function -: idle inserted for wait : short path 200 user ? s manual u14559ej2v0um appendix a instruction list the instruction function list in alphabetical order is shown in table a-1, and instruction list in format order is shown in table a-2. table a-1. instruction function list (in alphabetical order) (1/11) flag mnemonic operand format cy ov s z sat instruction function add reg1, reg2 i 0/1 0/1 0/1 0/1 ? add. adds the word data of reg1 to the word data of reg2, and stores the result to reg2. add imm5, reg2 ii 0/1 0/1 0/1 0/1 ? add. adds the 5-bit immediate data, sign- extended to word length, to the word data of reg2, and stores the result to reg2. addi imm16, reg1, reg2 vi 0/1 0/1 0/1 0/1 ? add immediate. adds the 16-bit immediate data, sign-extended to word length, to the word data of reg1, and stores the result to reg2. and reg1, reg2 i ? 00/10/1 ? and. ands the word data of reg2 with the word data of reg1, and stores the result to reg2. andi imm16, reg1, reg2 vi ? 00/10/1 ? and. ands the word data of reg1 with the 16- bit immediate data, zero-extended to word length, and stores the result to reg2. bcond disp9 iii ???? ? branch on condition code. tests a condition flag specified by an instruction. branches if a specified condition is satisfied; otherwise, executes the next instruction. the branch destination pc holds the sum of the current pc value and 9-bit displacement which is the 8-bit immediate shifted 1 bit and sign- extended to word length. bsh reg2, reg3 xii 0/1 0 0/1 0/1 ? byte swap half-word. performs endian conversion. bsw reg2, reg3 xii 0/1 0 0/1 0/1 ? byte swap word. performs endian conversion. callt imm6 ii ???? ? call with table look up. based on ctbp contents, updates pc value and transfers control. clr1 bit#3, disp16 [reg1] viii ??? 0/1 ? clear bit. adds the data of reg1 to a 16-bit displacement, sign-extended to word length, to generate a 32-bit address. then clears the bit, specified by the instruction bit field, of the byte data referenced by the generated address. appendix a instruction list 201 user ? s manual u14559ej2v0um table a-1. instruction function list (in alphabetical order) (2/11) flag mnemonic operand format cy ov s z sat instruction function clr1 reg2 [reg1] ix ??? 0/1 ? clear bit. first, reads the data of reg1 to generate a 32-bit address. then clears the bit, specified by the data of lower 3 bits of reg2 of the byte data referenced by the generated address. cmov cccc, r eg1, reg2, reg3 xi ???? ? conditional move. reg3 is set to reg1 if a condition specified by condition code ? cccc? is satisfied; otherwise, set to the data of reg2. cmov cccc, imm5, r eg2, reg3 xii ???? ? conditional move. reg3 is set to the data of 5- immediate, sign-extended to word length, if a condition specified by condition code ? cccc? is satisfied; otherwise, set to the data of reg2. cmp reg1, reg2 i 0/1 0/1 0/1 0/1 ? compare. compares the word data of reg2 with the word data of reg1, and indicates the result by using the psw flags. to compare, the contents of reg1 are subtracted from the word data of reg2. cmp imm5, reg2 ii 0/1 0/1 0/1 0/1 ? compare. compares the word data of reg2 with the 5-bit immediate data, sign-extended to word length, and indicates the result by using the psw flags. to compare, the contents of the sign-extended immediate data are subtracted from the word data of reg2. ctret (none) x 0/1 0/1 0/1 0/1 0/1 restore from callt. restores the restore pc and psw from the appropriate system register and restores from a routine called by callt. dbret note (none) x 0/1 0/1 0/1 0/1 0/1 return from debug trap. restores the restore pc and psw from the appropriate system register and restores from a debug monitor routine. dbtrap note (none) i ???? ? debug trap. saves the restore pc and psw to the appropriate system register and transfers control by setting the pc to handler address (00000060h). di (none) x ???? ? disables interrupt. sets the id flag of the psw to 1 to disable the acknowledgement of maskable interrupts from acceptance; interrupts are immediately disabled at the start of this instruction execution. dispose imm5, list12 xiii ???? ? function dispose. adds the data of 5-bit immediate imm5, logically shifted left by 2 and zero-extended to word length, to sp. then pop (load data from the address specified by sp and adds 4 to sp) general registers listed in list12. note not supported in the nb85e and nb85et appendix a instruction list 202 user ? s manual u14559ej2v0um table a-1. instruction function list (in alphabetical order) (3/11) flag mnemonic operand format cy ov s z sat instruction function dispose imm5, list12, [reg1] xiii ???? ? function dispose. adds the data of 5-bit immediate imm5, logically shifted left by 2 and zero-extended to word length, to sp. then pop (load data from the address specified by sp and adds 4 to sp) general registers listed in list12, transfers control to the address specified by reg1. div reg1, reg2, reg3 xi ? 0/1 0/1 0/1 ? divide word. divides the word data of reg2 by the word data of reg1, and stores the quotient to reg2 and the remainder to reg3. divh reg1, reg2 i ? 0/1 0/1 0/1 ? divide half-word. divides the word data of reg2 by the lower half-word data of reg1, and stores the quotient to reg2. divh reg1, reg2, reg3 xi ? 0/1 0/1 0/1 ? divide half-word. divides word data of reg2 by lower half-word data of reg1, and stores the quotient to reg2 and the remainder to reg3. divhu reg1, reg2, reg3 xi ? 0/1 0/1 0/1 ? divide half-word unsigned. divides word data of reg2 by lower half-word data of reg1, and stores the quotient to reg2 and the remainder to reg3. divu reg1, reg2, reg3 xi ? 0/1 0/1 0/1 ? divide word unsigned. divides the word data of reg2 by the word data of reg1, and stores the quotient to reg2 and the remainder to reg3. ei (none) x ???? ? enable interrupt. clears the id flag of the psw to 0 and enables the acknowledgement of maskable interrupts at the beginning of next instruction. halt (none) x ???? ? halt. stops the operating clock of the cpu and places the cpu in the halt mode. hsw reg2, reg3 xii 0/1 0 0/1 0/1 ? half-word swap word. performs endian conversion. jarl disp22, reg2 v ???? ? jump and register link. saves the current pc value plus 4 to general register reg2, adds a 22-bit displacement, sign-extended to word length, to the current pc value, and transfers control to the pc. bit 0 of the 22-bit displacement is masked to 0. jmp [reg1] i ???? ? jump register. transfers control to the address specified by reg1. bit 0 of the address is masked to 0. jr disp22 v ???? ? jump relative. adds a 22-bit displacement, sign-extended to word length, to the current pc value, and transfers control to the pc. bit 0 of the 22-bit displacement is masked to 0. appendix a instruction list 203 user ? s manual u14559ej2v0um table a-1. instruction function list (in alphabetical order) (4/11) flag mnemonic operand format cy ov s z sat instruction function ld.b disp16 [reg1], reg2 vii ???? ? byte load. adds the data of reg1 to a 16-bit displacement, sign-extended to word length, to generate a 32-bit address. byte data is read from the generated address, sign-extended to word length, and then stored to reg2. ld.bu disp16 [reg1], reg2 vii ???? ? unsigned byte load. adds the data of reg1 and the 16-bit displacement sign-extended to word length, and generates a 32-bit address. then reads the byte data from the generated address, zero-extends it to word length, and stores it to reg2. ld.h disp16 [reg1], reg2 vii ???? ? half-word load. adds the data of reg1 to a 16- bit displacement, sign-extended to word length, to generate a 32-bit address. half-word data is read from this 32-bit address with bit 0 masked to 0, sign-extended to word length, and stored to reg2. ld.hu disp16 [reg1], reg2 vii ???? ? unsigned half-word load. adds the data of reg1 and the 16-bit displacement sign- extended to word length to generate a 32-bit address. reads the half-word data from the address masking bit 0 of this 32-bit address to 0, zero-extends it to word length, and stores it to reg2. ld.w disp16 [reg1], reg2 vii ???? ? word load. adds the data of reg1 to a 16-bit displacement, sign-extended to word length, to generate a 32-bit address. word data is read from this 32-bit address with bits 0 and 1 masked to 0, and stored to reg2. ldsr reg2, regid ix ???? ? load to system register. set the word data of reg2 to a system register specified by regid. if regid is psw, the values of the corresponding bits of reg2 are set to the respective flags of the psw. mov reg1, reg2 i ???? ? move. transfers the word data of reg1 to reg2. mov imm5, reg2 ii ???? ? move. transfers the value of a 5-bit immediate data, sign-extended to word length, to reg2. mov imm32, reg1 vi ???? ? move. transfers the 32-bit immediate data to reg1. movea imm16, reg1, reg2 vi ???? ? move effective address. adds a 16-bit immediate data, sign-extended to word length, to the word data of reg1, and stores the result to reg2. appendix a instruction list 204 user ? s manual u14559ej2v0um table a-1. instruction function list (in alphabetical order) (5/11) flag mnemonic operand format cy ov s z sat instruction function movhi imm16, reg1, reg2 vi ???? ? move high half-word. adds word data, in which the higher 16 bits are defined by the 16- bit immediate data while the lower 16 bits are set to 0, to the word data of reg1 and stores the result to reg2. mul reg1, reg2, reg3 xi ???? ? multiply word. multiplies the word data of reg2 by the word data of reg1, and stores the result to reg2 and reg3 as double-word data. mul imm9, reg2, reg3 xii ???? ? multiply word. multiplies the word data of reg2 by the 9-bit immediate data sign-extended to word length, and stores the result to reg2 and reg3. mulh reg1, reg2 i ???? ? multiply half-word. multiplies the lower half- word data of reg2 by the lower half-word data of reg1, and stores the result to reg2 as word data. mulh imm5, reg2 ii ???? ? multiply half-word. multiplies the lower half- word data of reg2 by a 5-bit immediate data, sign-extended to half-word length, and stores the result to reg2 as word data. mulhi imm16, reg1, reg2 vi ???? ? multiply half-word immediate. multiplies the lower half-word data of reg1 by a 16-bit immediate data, and stores the result to reg2. mulu reg1, reg2, reg3 xi ???? ? multiply word unsigned. multiplies the word data of reg2 by the word data of reg1, and stores the result to reg2 and reg3 as double- word data. reg1 is not affected. mulu imm9, reg2, reg3 xii ???? ? multiply word unsigned. multiplies the word data of reg2 by the 9-bit immediate data sign- extended to word length, and store the result to reg2 and reg3. nop (none) i ???? ? no operation. not reg1, reg2 i ? 00/10/1 ? not. logically negates (takes 1?s complement of) the word data of reg1, and stores the result to reg2. not1 bit#3, disp16 [reg1] viii ??? 0/1 ? not bit. first, adds the data of reg1 to a 16-bit displacement, sign-extended to word length, to generate a 32-bit address. the bit specified by the 3-bit bit number is inverted at the byte data location referenced by the generated address. not1 reg2, [reg1] ix ??? 0/1 ? not bit. first, reads reg1 to generate a 32-bit address. the bit specified by the lower 3 bits of reg2 of the byte data of the generated address is inverted. appendix a instruction list 205 user ? s manual u14559ej2v0um table a-1. instruction function list (in alphabetical order) (6/11) flag mnemonic operand format cy ov s z sat instruction function or reg1, reg2 i ? 00/10/1 ? or. ors the word data of reg2 with the word data of reg1, and stores the result to reg2. ori imm16, reg1, reg2 vi ? 00/10/1 ? or immediate. ors the word data of reg1 with the 16-bit immediate data, zero-extended to word length, and stores the result to reg2. prepare list12, imm5 xiii ???? ? function prepare. the general register displayed in list12 is saved (4 is subtracted from sp, and the data is stored to that address). next, the data is logically shifted 2 bits to the left, and the 5-bit immediate data zero-extended to word length is subtracted from sp. prepare list12, imm5, sp/imm xiii ???? ? function prepare. the general register displayed in list12 is saved (4 is subtracted from sp, and the data is stored to that address). next, the data is logically shifted 2 bits to the left, and the 5-bit immediate data zero-extended to word length is subtracted from sp. then, the data specified by the third operand is loaded to ep. reti (none) x 0/1 0/1 0/1 0/1 0/1 return from trap or interrupt. reads the restore pc and psw from the appropriate system register, and restores from interrupt or exception processing routine. sar reg1, reg2 ix 0/1 0 0/1 0/1 ? shift arithmetic right. arithmetically shifts the word data of reg2 to the right by ?n? positions, where ?n? is specified by the lower 5 bits of reg1 (the msb prior to shift execution is copied and set as the new msb), and then writes the result to reg2. sar imm5, reg2 ii 0/1 0 0/1 0/1 ? shift arithmetic right. arithmetically shifts the word data of reg2 to the right by ?n? positions specified by the lower 5-bit immediate data, zero-extended to word length (the msb prior to shift execution is copied and set as the new msb), and then writes the result to reg2. sasf cccc, reg2 ix ???? ? shift and set flag condition. reg2 is logically shifted left by 1, and its lsb is set to 1 in a condition specified by condition code ? cccc? is satisfied; otherwise, lsb is set to 0. appendix a instruction list 206 user ? s manual u14559ej2v0um table a-1. instruction function list (in alphabetical order) (7/11) flag mnemonic operand format cy ov s z sat instruction function satadd reg1, reg2 i 0/1 0/1 0/1 0/1 0/1 saturated add. adds the word data of reg1 to the word data of reg2, and stores the result to reg2. however, if the result exceeds the maximum positive value, the maximum positive value is stored to reg2; if the result exceeds the maximum negative value, the maximum negative value is stored to reg2. the sat flag is set to 1. satadd imm5, reg2 ii 0/1 0/1 0/1 0/1 0/1 saturated add. adds the 5-bit immediate data, sign-extended to word length, to the word data of reg2, and stores the result to reg2. however, if the result exceeds the maximum positive value, the maximum positive value is stored to reg2; if the result exceeds the maximum negative value, the maximum negative value is stored to reg2. the sat flag is set to 1. satsub reg1, reg2 i 0/1 0/1 0/1 0/1 0/1 saturated subtract. subtracts the word data of reg1 from the word data of reg2, and stores the result to reg2. however, if the result exceeds the maximum positive value, the maximum positive value is stored to reg2; if the result exceeds the maximum negative value, the maximum negative value is stored to reg2. the sat flag is set to 1. satsubi imm16, reg1, reg2 vi 0/1 0/1 0/1 0/1 0/1 saturated subtract immediate. subtracts a 16-bit immediate data, sign-extended to word length, from the word data of reg1, and stores the result to reg2. however, if the result exceeds the maximum positive value, the maximum positive value is stored to reg2; if the result exceeds the maximum negative value, the maximum negative value is stored to reg2. the sat flag is set to 1. satsubr reg1, reg2 i 0/1 0/1 0/1 0/1 0/1 saturated subtract reverse. subtracts the word data of reg2 from the word data of reg1, and stores the result to reg2. however, if the result exceeds the maximum positive value, the maximum positive value is stored to reg2; if the result exceeds the maximum negative value, the maximum negative value is stored to reg2. the sat flag is set to 1. set1 bit#3, disp16 [reg1] viii ??? 0/1 ? set bit. first, adds a 16-bit displacement, sign-extended to word length, to the data of reg1 to generate a 32-bit address. the bits, specified by the 3-bit bit number, are set at the byte data location specified by the generated address. appendix a instruction list 207 user ? s manual u14559ej2v0um table a-1. instruction function list (in alphabetical order) (8/11) flag mnemonic operand format cy ov s z sat instruction function set1 reg2, [reg1] ix ??? 0/1 ? set bit. first, reads the data of general register reg1 to generate a 32-bit address. the bit, specified by the data of lower 3 bits of reg2, is set at the byte data location referenced by the generated address. setf cccc, reg2 ix ???? ? set flag condition. the reg2 is set to 1 if a condition specified by condition code " cccc" is satisfied; otherwise, a 0 is stored to reg2. shl reg1, reg2 ix 0/1 0 0/1 0/1 ? shift logical left. logically shifts the word data of reg2 to the left by ?n? positions (0 is shifted to the lsb side), where ?n? is specified by the lower 5 bits of reg1, and then writes the result to reg2. shl imm5, reg2 ii 0/1 0 0/1 0/1 ? shift logical left. logically shifts the word data of reg2 to the left by ?n? positions (0 is shifted to the lsb side), where ?n? is specified by a 5-bit immediate data, zero-extended to word length, and then writes the result to reg2. shr reg1, reg2 ix 0/1 0 0/1 0/1 ? shift logical right. logically shifts the word data of reg2 to the right by ?n? positions (0 is shifted to the msb side), where ?n? is specified by the lower 5 bits of reg1, and then writes the result to reg2. shr imm5, reg2 ii 0/1 0 0/1 0/1 ? shift logical right. logically shifts the word data of reg2 to the right by ?n? positions (0 is shifted to the msb side), where ?n? is specified by a 5-bit immediate data, zero-extended to word length, and then writes the result to reg2. sld.b disp7 [ep], reg2 iv ???? ? byte load. adds the 7-bit displacement, zero- extended to word length, to the element pointer to generate a 32-bit address. byte data is read from the generated address, sign- extended to word length, and then stored to reg2. sld.bu disp4 [ep], reg2 iv ???? ? unsigned byte load. adds the 4-bit displacement, zero-extended to word length, to the element pointer to generate a 32-bit address. byte data is read from the generated address, zero-extended to word length, and stored to reg2. sld.h disp8 [ep], reg2 iv ???? ? half-word load. adds the 8-bit displacement, zero-extended to word length, to the element pointer to generate a 32-bit address. half-word data is read from this 32-bit address with bit 0 masked to 0, sign-extended to word length, and stored to reg2. appendix a instruction list 208 user ? s manual u14559ej2v0um table a-1. instruction function list (in alphabetical order) (9/11) flag mnemonic operand format cy ov s z sat instruction function sld.hu disp5 [ep], reg2 iv ???? ? unsigned half-word load. adds the 5-bit displacement, zero-extended to word length, to the element pointer to generate a 32-bit address. half-word data is read from this 32- bit address with bit 0 masked to 0, zero- extended to word length, and stored to reg2. sld.w disp8 [ep], reg2 iv ???? ? word load. adds the 8-bit displacement, zero- extended to word length, to the element pointer to generate a 32-bit address. word data is read from this 32-bit address with bits 0 and 1 masked to 0, and stored to reg2. sst.b reg2, disp7 [ep] iv ???? ? byte store. adds the 7-bit displacement, zero- extended to word length, to the element pointer to generate a 32-bit address, and stores the data of the lowest byte of reg2 to the generated address. sst.h reg2, disp8 [ep] iv ???? ? half-word store. adds the 8-bit displacement, zero-extended to word length, to the element pointer to generate a 32-bit address, and stores the lower half-word of reg2 to the generated 32-bit address with bit 0 masked to 0. sst.w reg2, disp8 [ep] iv ???? ? word store. adds the 8-bit displacement, zero-extended to word length, to the element pointer to generate a 32-bit address, and stores the word data of reg2 to the generated 32-bit address with bits 0 and 1 masked to 0. st.b reg2, disp16 [reg1] vii ???? ? byte store. adds the 16-bit displacement, sign-extended to word length, to the data of reg1 to generate a 32-bit address, and stores the lowest byte data of reg2 to the generated address. st.h reg2, disp16 [reg1] vii ???? ? half-word store. adds the 16-bit displacement, sign-extended to word length, to the data of reg1 to generate a 32-bit address, and stores the lower half-word of reg2 to the generated 32-bit address with bit 0 masked to 0. st.w reg2, disp16 [reg1] vii ???? ? word store. adds the 16-bit displacement, sign-extended to word length, to the data of reg1 to generate a 32-bit address, and stores the word data of reg2 to the generated 32-bit address with bits 0 and 1 masked to 0. stsr regid, reg2 ix ???? ? store contents of system register. stores the contents of a system register specified by regid to reg2. appendix a instruction list 209 user ? s manual u14559ej2v0um table a-1. instruction function list (in alphabetical order) (10/11) flag mnemonic operand format cy ov s z sat instruction function sub reg1, reg2 i 0/1 0/1 0/1 0/1 ? subtract. subtracts the word data of reg1 from the word data of reg2, and stores the result to reg2. subr reg1, reg2 i 0/1 0/1 0/1 0/1 ? subtract reverse. subtracts the word data of reg2 from the word data of reg1, and stores the result to reg2. switch reg1 i ???? ? jump with table look up. adds the table entry address (address following switch instruction) and data of reg1 logically shifted to the left by 1 bit, and loads the half-word entry data specified by the table entry address. next, logically shifts to the left by 1 bit the loaded data, and after sign-extending it to word length, branches to the target address added to the table entry address (instruction following switch instruction). sxb reg1 i ???? ? sign extend byte. sign-extends the lowermost byte of reg1 to word length. sxh reg1 i ???? ? sign extend half-word. sign-extends lower half-word of reg1 to word length. trap vector x ???? ? trap. saves the restore pc and psw; sets the exception code and the flags of the psw; jumps to the address of the trap handler corresponding to the trap vector specified by vector, and starts exception processing. tst reg1, reg2 i ? 00/10/1 ? test. ands the word data of reg2 with the word data of reg1. the result is not stored, and only the flags are changed. tst1 bit#3, disp16 [reg1] viii ??? 0/1 ? test bit. adds the data of reg1 to a 16-bit displacement, sign-extended to word length, to generate a 32-bit address. performs the test on the bit, specified by the 3-bit bit number, at the byte data location referenced by the generated address. if the specified bit is 0, the z flag is set to 1; if the bit is 1, the z flag is cleared to 0. tst1 reg2, [reg1] ix ??? 0/1 ? test bit. first, reads the data of reg1 to generate a 32-bit address. if the bits indicated by the lower 3 bits of reg2 of the byte data of the generated address are 0, the z flag is set to 1, and if they are 1, the z flag is cleared to 0. xor reg1, reg2 i ? 00/10/1 ? exclusive or. exclusively ors the word data of reg2 with the word data of reg1, and stores the result to reg2. appendix a instruction list 210 user ? s manual u14559ej2v0um table a-1. instruction function list (in alphabetical order) (11/11) flag mnemonic operand format cy ov s z sat instruction function xori imm16, reg1, reg2 vi ? 00/10/1 ? exclusive or immediate. exclusively ors the word data of reg1 with a 16-bit immediate data, zero-extended to word length, and stores the result to reg2. zxb reg1 i ???? ? zero extend byte. zero-extends to word length the lowest byte of reg1. zxh reg1 i ???? ? zero extend half-word. zero-extends to word length the lower half-word of reg1. appendix a instruction list 211 user ? s manual u14559ej2v0um table a-2. instruction list (in format order) (1/3) opcode format 15 0 31 16 mnemonic operand 0000000000000000 ?nop ? rrrrr000000rrrrr ? mov reg1, reg2 rrrrr000001rrrrr ? not reg1, reg2 rrrrr000010rrrrr ? divh reg1, reg2 00000000010rrrrr ? switch reg1 00000000011rrrrr ? jmp [reg1] rrrrr000100rrrrr ? satsubr reg1, reg2 rrrrr000101rrrrr ? satsub reg1, reg2 rrrrr000110rrrrr ? satadd reg1, reg2 rrrrr000111rrrrr ? mulh reg1, reg2 00000000100rrrrr ? zxb reg1 00000000101rrrrr ? sxb reg1 00000000110rrrrr ? zxh reg1 00000000111rrrrr ? sxh reg1 rrrrr001000rrrrr ? or reg1, reg2 rrrrr001001rrrrr ? xor reg1, reg2 rrrrr001010rrrrr ? and reg1, reg2 rrrrr001011rrrrr ? tst reg1, reg2 rrrrr001100rrrrr ? subr reg1, reg2 rrrrr001101rrrrr ? sub reg1, reg2 rrrrr001110rrrrr ? add reg1, reg2 rrrrr001111rrrrr ? cmp reg1, reg2 i 1111100001000000 ? dbtrap note ? rrrrr010000iiiii ? mov imm5, reg2 rrrrr010001iiiii ? satadd imm5, reg2 rrrrr010010iiiii ? add imm5, reg2 rrrrr010011iiiii ? cmp imm5, reg2 0000001000iiiiii ? callt imm6 rrrrr010100iiiii ? shr imm5, reg2 rrrrr010101iiiii ? sar imm5, reg2 rrrrr010110iiiii ? shl imm5, reg2 ii rrrrr010111iiiii ? mulh imm5, reg2 iii ddddd1011dddcccc ? bcond disp9 note not supported in the nb85e and nb85et appendix a instruction list 212 user ? s manual u14559ej2v0um table a-2. instruction list (in format order) (2/3) opcode format 15 0 31 16 mnemonic operand rrrrr0000110dddd ? sld.bu disp4 [ep], reg2 rrrrr0000111dddd ? sld.hu disp5 [ep], reg2 rrrrr0110ddddddd ? sld.b disp7 [ep], reg2 rrrrr0111ddddddd ? sst.b reg2, disp7 [ep] rrrrr1000ddddddd ? sld.h disp8 [ep], reg2 rrrrr1001ddddddd ? sst.h reg2, disp8 [ep] rrrrr1010dddddd0 ? sld.w disp8 [ep], reg2 iv rrrrr1010dddddd1 ? sst.w reg2, disp8 [ep] rrrrr11110dddddd ddddddddddddddd0 jarl disp22, reg2 v 0000011110dddddd ddddddddddddddd0 jr disp22 rrrrr110000rrrrr iiiiiiiiiiiiiiii addi imm16, reg1, reg2 rrrrr110001rrrrr iiiiiiiiiiiiiiii movea imm16, reg1, reg2 rrrrr110010rrrrr iiiiiiiiiiiiiiii movhi imm16, reg1, reg2 rrrrr110011rrrrr iiiiiiiiiiiiiiii satsubi imm16, reg1, reg2 00000110001rrrrr note mov imm32, reg1 rrrrr110100rrrrr iiiiiiiiiiiiiiii ori imm16, reg1, reg2 rrrrr110101rrrrr iiiiiiiiiiiiiiii xori imm16, reg1, reg2 rrrrr110110rrrrr iiiiiiiiiiiiiiii andi imm16, reg1, reg2 vi rrrrr110111rrrrr iiiiiiiiiiiiiiii mulhi imm16, reg1, reg2 rrrrr111000rrrrr dddddddddddddddd ld.b disp16 [reg1], reg2 rrrrr111001rrrrr ddddddddddddddd0 ld.h disp16 [reg1], reg2 rrrrr111001rrrrr ddddddddddddddd1 ld.w disp16 [reg1], reg2 rrrrr111010rrrrr dddddddddddddddd st.b reg2, disp16 [reg1] rrrrr111011rrrrr ddddddddddddddd0 st.h reg2, disp16 [reg1] rrrrr111011rrrrr ddddddddddddddd1 st.w reg2, disp16 [reg1] rrrrr11110brrrrr ddddddddddddddd1 ld.bu disp16 [reg1], reg2 vii rrrrr111111rrrrr ddddddddddddddd1 ld.hu disp16 [reg1], reg2 00bbb111110rrrrr dddddddddddddddd set1 bit#3, disp16 [reg1] 01bbb111110rrrrr dddddddddddddddd not1 bit#3, disp16 [reg1] 10bbb111110rrrrr dddddddddddddddd clr1 bit#3, disp16 [reg1] viii 11bbb111110rrrrr dddddddddddddddd tst1 bit#3, disp16 [reg1] note 32-bit immediate data. the higher 32 bits (bits 16 to 47) are as follows. 31 16 47 32 iiiiiiiiiiiiiiii iiiiiiiiiiiiiiii appendix a instruction list 213 user ? s manual u14559ej2v0um table a-2. instruction list (in format order) (3/3) opcode format 15 0 31 16 mnemonic operand rrrrr1111110cccc 0000000000000000 setf cccc, reg2 rrrrr111111rrrrr 0000000000100000 ldsr reg2, regid rrrrr111111rrrrr 0000000001000000 stsr regid, reg2 rrrrr111111rrrrr 0000000010000000 shr reg1, reg2 rrrrr111111rrrrr 0000000010100000 sar reg1, reg2 rrrrr111111rrrrr 0000000011000000 shl reg1, reg2 rrrrr111111rrrrr 0000000011100000 set1 reg2, [reg1] rrrrr111111rrrrr 0000000011100010 not1 reg2, [reg1] rrrrr111111rrrrr 0000000011100100 clr1 reg2, [reg1] rrrrr111111rrrrr 0000000011100110 tst1 reg2, [reg1] ix rrrrr1111110cccc 0000001000000000 sasf cccc, reg2 00000111111iiiii 0000000100000000 trap vector 0000011111100000 0000000100100000 halt ? 0000011111100000 0000000101000000 reti ? 0000011111100000 0000000101000100 ctret ? 0000011111100000 0000000101000110 dbret note ? 0000011111100000 0000000101100000 di ? x 1000011111100000 0000000101100000 ei ? rrrrr111111rrrrr wwwww01000100000 mul reg1, reg2, reg3 rrrrr111111rrrrr wwwww01000100010 mulu reg1, reg2, reg3 rrrrr111111rrrrr wwwww01010000000 divh reg1, reg2, reg3 rrrrr111111rrrrr wwwww01010000010 divhu reg1, reg2, reg3 rrrrr111111rrrrr wwwww01011000000 div reg1, reg2, reg3 rrrrr111111rrrrr wwwww01011000010 divu reg1, reg2, reg3 xi rrrrr111111rrrrr wwwww011001cccc0 cmov cccc, r eg1, reg2, reg3 rrrrr111111iiiii wwwww01001iiii00 mul imm9, reg2, reg3 rrrrr111111iiiii wwwww01001iiii10 mulu imm9, reg2, reg3 rrrrr111111iiiii wwwww011000cccc0 cmov cccc, imm5, r eg2, reg3 rrrrr11111100000 wwwww01101000000 bsw reg2, reg3 rrrrr11111100000 wwwww01101000010 bsh reg2, reg3 xii rrrrr11111100000 wwwww01101000100 hsw reg2, reg3 0000011001iiiiil lllllllllllrrrrr dispose imm5, list12, [reg1] 0000011001iiiiil lllllllllll00000 dispose imm5, list12 0000011110iiiiil lllllllllll00001 prepare list12, imm5 xiii 0000011110iiiiil lllllllllllff011 prepare list12, imm5, sp/imm note not supported in the nb85e and nb85et 214 user?s manual u14559ej2v0um appendix b instruction opcode map this chapter shows the opcode map for the instruction code shown below. (1) 16-bit format instruction 15 5 0 11 10 sub-opcode (see [b]) 4 opcode (see [a]) (2) 32-bit format instruction 15 5 0 11 10 31 16 20 21 4 14 13 12 26 27 19 18 17 sub-opcode (see [h]) opcode (see [a]) sub-opcode (see [e]) sub-opcode (see [d], [h]) sub-opcode (see [c]) sub-opcode (see [f], [g], [i]) remark operand convention symbol meaning r reg1: general register (used as source register) r reg2: general register (mainly used as destination register. some are also used as source registers.) w reg3: general register (mainly used as remainder of division results or higher 32 bits of multiply results) bit#3 3-bit data for bit number specification imm -bit immediate data disp -bit displacement data cccc 4-bit data c ondition code specification appendix b instruction opcode map 215 user?s manual u14559ej2v0um [a] opcode bit bit bit bit bits 6, 5 10 9 8 7 0,0 0,1 1,0 1,1 format 0000mov r, r nop note 1 not divh switch note 2 dbtrap undefined note 3 jmp note 4 sld.bu note 5 sld.hu note 6 i, iv 0 0 0 1 satsubr zxb note 4 satsub sxb note 4 satadd r, r zxh note 4 mulh sxh note 4 0010or xor and tst 0 0 1 1 subr sub add r, r cmp r, r i mov imm5, r satadd imm5, r 0100 callt note 4 add imm5, r cmp imm5, r 0 1 0 1 shr imm5, r sar imm5, r shl imm5, r mulh imm5, r undefined note 4 ii 0110sld.b 0111sst.b 1000sld.h 1001sst.h 1010 sld.w note 7 sst.w note 7 iv 1011bcond iii movhi satsubi 1 1 0 0 addi movea mov imm32, r note 4 dispose note 4 vi, xiii 1 1 0 1 ori xori andi mulhi undefined note 4 vi 1110ld.b ld.h note 8 ld.w note 8 st.b st.h note 8 st.w note 8 vii 1111jr jarl ld.bu note 10 prepare note 11 bit manipulation 1 note 9 ld.hu note 10 undefined note 11 expansion 1 note 12 v, vii, viii, xiii notes 1. if r (reg1) = r0 and r (reg2) = r0 (instruction without reg1 and reg2) 2. if r (reg1) r0 and r (reg2) = r0 (instruction with reg1 and without reg2) 3. if r (reg1) = r0 and r (reg2) r0 (instruction without reg1 and with reg2) 4. if r (reg2) = r0 (instruction without reg2) 5. if bit 4 = 0 and r (reg2) r0 (instruction with reg2) 6. if bit 4 = 1 and r (reg2) r0 (instruction with reg2) 7. see [b] 8. see [c] 9. see [d] 10. if bit 16 = 1 and r (reg2) r0 (instruction with reg2) 11. if bit 16 = 1 and r (reg2) = r0 (instruction without reg2) 12. see [e] remark the nb85e and nb85et do not support the dbtrap instruction. appendix b instruction opcode map 216 user?s manual u14559ej2v0um [b] short format load/store instruction (displacement/sub-opcode) bit 0 bit 10 bit 9 bit 8 bit 7 01 0110sld.b 0111sst.b 1000sld.h 1001sst.h 1 0 1 0 sld.w sst.w [c] load/store instruction (displacement/sub-opcode) bit 16 bit 6 bit 5 01 00ld.b 0 1 ld.h ld.w 10st.b 1 1 st.h st.w [d] bit manipulation instruction 1 (sub-opcode) bit 14 bit 15 01 0 set1 bit#3, disp16 [r] not1 bit#3, disp16 [r] 1 clr1 bit#3, disp16 [r] tst1 bit#3, disp16 [r] appendix b instruction opcode map 217 user?s manual u14559ej2v0um [e] expansion 1 (sub-opcode) bits 22, 21 bit 26 bit 25 bit 24 bit 23 0,0 0,1 1,0 1,1 format 0 0 0 0 setf ldsr stsr undefined 0 0 0 1 shr sar shl bit manipulation 2 note 1 ix 0010trap halt reti note 2 ctret note 2 dbret note 2 undefined ei note 3 di note 3 undefined x 0 0 1 1 undefined undefined ? 0 1 0 0 sasf mul r, r, w mulu r, r, w note 4 mul imm9, r, w mulu imm9, r, w note 4 ix, xi, xii 0101divh divhu note 4 div divu note 4 xi 0110cmov cccc, imm5, r, w cmov cccc, r, r, w bsw note 5 bsh note 5 hsw note 5 undefined xi, xii 0111 1xxx illegal instruction ? notes 1. see [f] 2. see [g] 3. see [h] 4. if bit 17 = 1 5. see [i] remark the nb85e and nb85et do not support the dbret instruction. [f] bit manipulation instruction 2 (sub-opcode) bit 17 bit 18 01 0 set1 r, [r] not1 r, [r] 1 clr1 r, [r] tst1 r, [r] [g] return instruction (sub-opcode) bit 17 bit 18 01 0 reti undefined 1 ctret dbret appendix b instruction opcode map 218 user?s manual u14559ej2v0um [h] psw operation instruction (sub-opcode) bits 13, 12, 11 bit 15 bit 14 0,0,0 0,0,1 0,1,0 0,1,1 1,0,0 1,0,1 1,1,0 1,1,1 0 0 di undefined 0 1 undefined 1 0 ei undefined 1 1 undefined [i] endian conversion instruction (sub-opcode) bit 17 bit 18 01 0 bsw bsh 1 hsw undefined 219 user ? s manual u14559ej2v0um appendix c differences with architecture of v850 cpu (1/2) item v850e1 cpu v850 cpu bsh reg2, reg3 bsw reg2, reg3 callt imm6 clr1 reg2, [reg1] cmov cccc, imm5, r eg2, reg3 cmov cccc, r eg1, reg2, reg3 ctret dbret note dbtrap note dispose imm5, list12 dispose imm5, list12 [reg1] div reg1, reg2, reg3 divh reg1, reg2, reg3 divhu reg1, reg2, reg3 divu reg1, reg2, reg3 hsw reg2, reg3 ld.bu disp16 [reg1], reg2 ld.hu disp16 [reg1], reg2 mov imm32, reg1 mul imm9, reg2, reg3 mul reg1, reg2, reg3 mulu reg1, reg2, reg3 mulu imm9, reg2, reg3 not1 reg2, [reg1] prepare list12, imm5 prepare list12, imm5, sp/imm sasf cccc, reg2 set1 reg2, [reg1] sld.bu disp4 [ep], reg2 sld.hu disp5 [ep], reg2 switch reg1 sxb reg1 sxh reg1 tst1 reg2, [reg1] zxb reg1 instructions (including operand) zxh reg1 provided not provided note not supported in the nb85e and nb85et appendix c differences with architecture of v850 cpu 220 user ? s manual u14559ej2v0um (2/2) item v850e1 cpu v850 cpu format iv format is different for some instructions. format xi format xii instruction format format xiii provided not provided instruction execution clocks value differs for some instructions. program space 64 mb linear 16 mb linear valid bits of program counter (pc) lower 26 bits lower 24 bits callt execution status saving registers (ctpc, ctpsw) exception/debug trap status saving registers (dbpc, dbpsw) callt base pointer (ctbp) debug interface register (dir) note 1 breakpoint control registers 0 and 1 (bpc0, bpc1) note 1 program id register (asid) note 1 breakpoint address setting registers 0 and 1 (bpav0, bpav1) note 1 breakpoint address mask registers 0 and 1 (bpam0, bpam1) note 1 breakpoint data setting registers 0 and 1 (bpdv0, bpdv1) note 1 breakpoint data mask registers 0 and 1 (bpdm0, bpdm1) note 1 provided not provided system register exception trap status saving registers dbpc, dbpsw eipc, eipsw illegal instruction code instruction code areas differ. misaligned access enable/disable setting can be set depending on product cannot be set. (misaligned access disabled) 3 (nb85e, nb85et, NU85E, NU85Et) input 1 (v850e/ma1, v850e/ma2, v850e/ia1, v850e/ia2) 1 exception code 0010h, 0020h, 0030h 0010h non-maskable interrupt (nmi) handler address 00000010h, 00000020h, 00000030h 00000010h debug trap note 2 provided not provided pipeline at next instruction, pipeline flow differs. ? arithmetic operation instruction ? branch instruction ? bit manipulation instruction ? special instruction (trap, reti) notes 1. used only for the NU85E and NU85Et 2. not supported in the nb85e and nb85et 221 user?s manual u14559ej2v0um appendix d instructions added for v850e1 cpu compared with v850 cpu compared with the instruction codes of the v850 cpu, the instruction codes of the v850e1 cpu are upward compatible at the object code level. in the case of the v850e1 cpu, instructions that even if executed have no meaning in the case of the v850 cpu (mainly instructions performing write to the r0 register) are extended as additional instructions. the following table shows the v850 cpu instructions corresponding to the instruction codes added in the v850e1 cpu. see the table when switching from products that incorporate the v850 cpu to products that incorporate the v850e1 cpu. table d-1. instructions added to v850e1 cpu and v850 cpu instructions with same instruction code (1/2) instructions added in v850e1 cpu v850 cpu instructions with same instruction code as v850e1 cpu callt imm6 mov imm5, r0 or satadd imm5, r0 dispose imm5, list12 movhi imm16, reg1, r0 or satsubi imm16, reg1, r0 dispose imm5, list12 [reg1] movhi imm16, r eg1, r0 or satsubi imm16, reg1, r0 mov imm32, reg1 movea imm16, reg1, r0 switch reg1 divh reg1, r0 sxb reg1 satsub reg1, r0 sxh reg1 mulh reg1, r0 zxb reg1 satsubr reg1, r0 zxh reg1 satadd reg1, r0 (rfu) mulh imm5, r0 (rfu) mulhi imm16, reg1, r0 bsh reg2, reg3 bsw reg2, reg3 cmov cccc, imm5, r eg2, reg3 cmov cccc, r eg1, reg2, reg3 ctret div reg1, reg2, reg3 divh reg1, reg2, reg3 divhu reg1, reg2, reg3 divu reg1, reg2, reg3 hsw reg2, reg3 mul imm9, reg2, reg3 mul reg1, reg2, reg3 mulu reg1, reg2, reg3 mulu imm9, reg2, reg3 sasf cccc, reg2 illegal instruction appendix d instructions added for v850e1 cpu compared with v850 cpu 222 user?s manual u14559ej2v0um table d-1. instructions added to v850e1 cpu and v850 cpu instructions with same instruction code (2/2) instructions added in v850e1 cpu v850 cpu instructions with same instruction code as v850e1 cpu clr1 reg2, [reg1] dbret note dbtrap note ld.bu disp16 [reg1], reg2 ld.hu disp16 [reg1], reg2 not1 reg2, [reg1] prepare list12, imm5 prepare list12, imm5, sp/imm set1 reg2, [reg1] sld.bu disp4 [ep], reg2 sld.hu disp5 [ep], reg2 tst1 reg2, [reg1] undefined note not supported in the nb85e and nb85et 223 user?s manual u14559ej2v0um appendix e index [numeral] 16-bit format instruction ........................................ 214 16-bit load/store instruction format ......................... 47 2-clock branch ...................................................... 180 3-operand instruction format ................................... 48 32-bit format instruction ........................................ 214 32-bit load/store instruction format ......................... 48 [a] add ........................................................................ 56 addi ....................................................................... 57 additional items related to pipeline ....................... 197 address space ........................................................ 40 addressing mode .................................................... 42 alignment hazard................................................... 193 and ........................................................................ 58 andi ....................................................................... 59 arithmetic operation instructions ............................. 51 arithmetic operation instructions (pipeline) ........... 184 asid ....................................................................... 33 [b] based addressing ................................................... 44 bcond ...................................................................... 60 bit ...................................................................... 37, 38 bit addressing ......................................................... 45 bit manipulation instruction format .......................... 48 bit manipulation instructions ................................... 52 bit manipulation instructions (pipeline) ................. 187 bpam0 .................................................................... 34 bpam1 .................................................................... 34 bpav0 .................................................................... 33 bpav1 .................................................................... 33 bpc0 ...................................................................... 31 bpc1 ...................................................................... 31 bpdm0 ................................................................... 35 bpdm1 ................................................................... 35 bpdv0 .................................................................... 34 bpdv1 .................................................................... 34 br instruction (pipeline) ........................................ 186 branch instructions ................................................. 52 branch instructions (pipeline) ............................... 185 breakpoint address mask registers 0 and 1 ........... 34 breakpoint address setting registers 0 and 1 ......... 33 breakpoint control registers 0 and 1 ....................... 31 breakpoint data mask registers 0 and 1 ................. 35 breakpoint data setting registers 0 and 1 ............... 34 bsh ........................................................................ 62 bsw ........................................................................ 63 byte ........................................................................ 37 [c] callt .................................................................... 64 callt base pointer ............................................... 29 callt caller status saving registers ...................... 28 callt instruction (pipeline) ................................. 187 cautions when creating programs ........................ 196 clr1 ...................................................................... 65 clr1 instruction (pipeline) ................................... 187 cmov ..................................................................... 66 cmp ........................................................................ 67 conditional branch instruction format ..................... 47 ctbp ...................................................................... 29 ctpc ...................................................................... 28 ctpsw ................................................................... 28 ctret .................................................................... 68 ctret instruction (pipeline) ................................ 188 [d] data alignment ....................................................... 39 data format ............................................................. 36 data representation ................................................ 38 data type ................................................................ 36 dbpc ...................................................................... 29 dbpsw .................................................................. 29 dbret ................................................................... 69 dbret instruction (pipeline) ................................ 192 dbtrap ................................................................. 70 dbtrap instruction (pipeline) .............................. 192 debug function instructions .................................... 53 debug function instructions (pipeline) .................. 192 debug interface register ......................................... 30 debug trap ............................................................ 172 di ............................................................................ 71 di instruction (pipeline) ......................................... 188 dir ......................................................................... 30 dispose ................................................................ 72 dispose instruction (pipeline) ............................ 189 div ......................................................................... 74 divh ....................................................................... 75 divhu .................................................................... 77 divide instructions (pipeline) ................................ 184 divu ....................................................................... 78 [e] ecr ........................................................................ 26 efficient pipeline processing ................................. 181 ei ............................................................................ 79 appendix e index 224 user?s manual u14559ej2v0um eipc ....................................................................... 25 eipsw .................................................................... 25 ei instruction (pipeline) ......................................... 188 exception cause register ........................................ 26 exception/debug trap status saving registers ......... 29 exception processing ........................................... 170 exception trap ....................................................... 171 extended instruction format 1 ................................. 48 extended instruction format 2 ................................. 49 extended instruction format 3 ................................. 49 extended instruction format 4 ................................. 49 [f] fepc ...................................................................... 26 fepsw ................................................................... 26 format i .................................................................. 46 format ii ................................................................. 46 format iii ................................................................ 47 format iv ................................................................ 47 format ix ................................................................ 48 format v ................................................................. 47 format vi ................................................................ 48 format vii ............................................................... 48 format viii .............................................................. 48 format x ................................................................. 49 format xi ................................................................ 49 format xii ............................................................... 49 format xiii .............................................................. 49 [g] general registers .................................................... 23 [h] half-word ................................................................ 37 halt ...................................................................... 80 halt instruction (pipeline) ................................... 189 harvard architecture ............................................. 197 hsw ....................................................................... 81 [i] imm-reg instruction format ...................................... 46 immediate addressing ............................................ 44 instruction address ................................................. 42 instruction format .................................................... 46 instruction opcode map ........................................ 214 instruction set ......................................................... 54 integer .................................................................... 38 internal configuration .............................................. 21 interrupt servicing ................................................. 167 interrupt status saving registers ............................. 25 [j] jarl .......................................................................82 jmp .........................................................................83 jmp instruction (pipeline) ......................................186 jr ............................................................................84 jump instruction format ...........................................47 [l] ld instructions ........................................................50 ld instructions (pipeline) ......................................182 ld.b ........................................................................85 ld.bu ......................................................................87 ld.h ........................................................................89 ld.hu .....................................................................91 ld.w .......................................................................93 ldsr .......................................................................95 ldsr instruction (pipeline) ...................................189 load instructions .....................................................50 load instructions (pipeline) ...................................182 logical operation instructions .................................51 logical operation instructions (pipeline) ................185 [m] maskable interrupt .................................................167 memory map ...........................................................41 mov ........................................................................96 movea ...................................................................97 move word instruction (pipeline) ...........................184 movhi ....................................................................98 mul .........................................................................99 mulh ....................................................................100 mulhi ...................................................................101 multiply instructions .................................................50 multiply instructions (pipeline) ...............................183 mulu ....................................................................102 [n] nmi status saving registers .....................................26 non-blocking load/store .........................................179 non-maskable interrupt .........................................169 nop ......................................................................103 nop instruction (pipeline) .....................................190 not .......................................................................104 not1 .....................................................................105 not1 instruction (pipeline) ...................................187 [o] operand address ....................................................44 or .........................................................................106 ori ........................................................................107 appendix e index 225 user?s manual u14559ej2v0um [p] pc ........................................................................... 23 pipeline ................................................................. 177 pipeline disorder ................................................... 193 pipeline flow during execution of instructions ....... 182 prepare.............................................................. 108 prepare instruction (pipeline) ........................... 190 program counter ...................................................... 23 program id register ................................................ 33 program registers ................................................... 23 program status word ............................................... 27 psw ........................................................................ 27 [r] r0 to r31 .................................................................. 23 reg-reg instruction format ........................................ 46 register addressing ................................................ 44 register addressing (register indirect) .................... 43 register set ............................................................. 23 register status after reset ..................................... 175 relative addressing (pc relative) ........................... 42 reset .................................................................... 175 restoring from exception trap and debug trap ..... 174 restoring from interrupt/exception processing ..... 173 reti ...................................................................... 110 reti instruction (pipeline) .................................... 190 [s] sar ...................................................................... 112 sasf .................................................................... 113 satadd ............................................................... 114 satsub ............................................................... 115 satsubi .............................................................. 116 satsubr ............................................................. 117 saturated operation instructions ............................. 51 saturated operation instructions (pipeline) ........... 185 set1 ..................................................................... 118 set1 instruction (pipeline) .................................... 187 setf ..................................................................... 119 shl ....................................................................... 121 short path ............................................................. 198 shr ...................................................................... 122 sld.b ................................................................... 123 sld.bu ................................................................. 125 sld.h ................................................................... 127 sld.hu ................................................................. 129 sld.w .................................................................. 131 sld instructions ...................................................... 50 sld instructions (pipeline) .................................... 182 software exception ............................................... 170 special instructions ................................................. 52 special instructions (pipeline) ............................... 187 sst.b ................................................................... 133 sst.h ................................................................... 135 sst.w .................................................................. 137 sst instructions ..................................................... 50 st.b ..................................................................... 139 st.h ..................................................................... 141 st.w .................................................................... 143 st instructions ........................................................ 50 stack manipulation instruction format 1 ................. 49 starting up ............................................................ 176 store instructions .................................................... 50 store instructions (pipeline) .................................. 183 stsr .................................................................... 145 stsr instruction (pipeline) ................................... 189 sub ...................................................................... 146 subr .................................................................... 147 switch ............................................................... 148 switch instruction (pipeline) .............................. 191 sxb ...................................................................... 149 sxh ...................................................................... 150 system registers ..................................................... 24 [t] trap .................................................................... 151 trap instruction (pipeline) ................................... 191 tst ....................................................................... 152 tst1 ..................................................................... 153 tst1 instruction (pipeline) ................................... 187 [u] unconditional branch instructions ........................ 186 unsigned integer .................................................... 38 [w] word ....................................................................... 36 [x] xor ...................................................................... 154 xori ..................................................................... 155 [z] zxb ...................................................................... 156 zxh ...................................................................... 157 226 user?s manual u14559ej2v0um [memo] although nec has taken all possible steps to ensure that the documentation supplied to our customers is complete, bug free and up-to-date, we readily accept that errors may occur. despite all the care and precautions we've taken, you may encounter problems in the documentation. please complete this form whenever you'd like to report errors or suggest improvements to us. hong kong, philippines, oceania nec electronics hong kong ltd. fax: +852-2886-9022/9044 korea nec electronics hong kong ltd. seoul branch fax: +82-2-528-4411 taiwan nec electronics taiwan ltd. fax: +886-2-2719-5951 address north america nec electronics inc. corporate communications dept. fax: +1-800-729-9288 +1-408-588-6130 europe nec electronics (europe) gmbh technical documentation dept. fax: +49-211-6503-274 south america nec do brasil s.a. fax: +55-11-6462-6829 asian nations except philippines nec electronics singapore pte. ltd. fax: +65-250-3583 japan nec semiconductor technical hotline fax: +81- 44-435-9608 i would like to report the following error/make the following suggestion: document title: document number: page number: thank you for your kind support. if possible, please fax the referenced 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